Affects Flags: N V Z C
MODE SYNTAX HEX LEN TIM Immediate ADC #44ドル 69ドル 2 2 Zero Page ADC 44ドル 65ドル 2 3 Zero Page,X ADC 44,ドルX 75ドル 2 4 Absolute ADC 4400ドル 6ドルD 3 4 Absolute,X ADC 4400,ドルX 7ドルD 3 4+ Absolute,Y ADC 4400,ドルY 79ドル 3 4+ Indirect,X ADC (44,ドルX) 61ドル 2 6 Indirect,Y ADC (44ドル),Y 71ドル 2 5+ + add 1 cycle if page boundary crossedADC results are dependant on the setting of the decimal flag. In decimal mode, addition is carried out on the assumption that the values involved are packed BCD (Binary Coded Decimal).
There is no way to add without carry.
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate AND #44ドル 29ドル 2 2 Zero Page AND 44ドル 25ドル 2 3 Zero Page,X AND 44,ドルX 35ドル 2 4 Absolute AND 4400ドル 2ドルD 3 4 Absolute,X AND 4400,ドルX 3ドルD 3 4+ Absolute,Y AND 4400,ドルY 39ドル 3 4+ Indirect,X AND (44,ドルX) 21ドル 2 6 Indirect,Y AND (44ドル),Y 31ドル 2 5+ + add 1 cycle if page boundary crossed
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Accumulator ASL A 0ドルA 1 2 Zero Page ASL 44ドル 06ドル 2 5 Zero Page,X ASL 44,ドルX 16ドル 2 6 Absolute ASL 4400ドル 0ドルE 3 6 Absolute,X ASL 4400,ドルX 1ドルE 3 7ASL shifts all bits left one position. 0 is shifted into bit 0 and the original bit 7 is shifted into the Carry.
Affects Flags: N V Z
MODE SYNTAX HEX LEN TIM Zero Page BIT 44ドル 24ドル 2 3 Absolute BIT 4400ドル 2ドルC 3 4BIT sets the Z flag as though the value in the address tested were ANDed with the accumulator. The N and V flags are set to match bits 7 and 6 respectively in the value stored at the tested address.
BIT is often used to skip one or two following bytes as in:
CLOSE1 LDX #10ドル If entered here, we .BYTE 2ドルC effectively perform CLOSE2 LDX #20ドル a BIT test on 20ドルA2, .BYTE 2ドルC another one on 30ドルA2, CLOSE3 LDX #30ドル and end up with the X CLOSEX LDA #12 register still at 10ドル STA ICCOM,X upon arrival here.Beware: a BIT instruction used in this way as a NOP does have effects: the flags may be modified, and the read of the absolute address, if it happens to access an I/O device, may cause an unwanted action.
Affect Flags: none
All branches are relative mode and have a length of two bytes. Syntax is "Bxx Displacement" or (better) "Bxx Label". See the notes on the Program Counter for more on displacements.
Branches are dependant on the status of the flag bits when the op code is encountered. A branch not taken requires two machine cycles. Add one if the branch is taken and add one more if the branch crosses a page boundary.
MNEMONIC HEX BPL (Branch on PLus) 10ドル BMI (Branch on MInus) 30ドル BVC (Branch on oVerflow Clear) 50ドル BVS (Branch on oVerflow Set) 70ドル BCC (Branch on Carry Clear) 90ドル BCS (Branch on Carry Set) $B0 BNE (Branch on Not Equal) $D0 BEQ (Branch on EQual) $F0There is no BRA (BRanch Always) instruction but it can be easily emulated by branching on the basis of a known condition. One of the best flags to use for this purpose is the oVerflow which is unchanged by all but addition and subtraction operations.
A page boundary crossing occurs when the branch destination is on a different page than the instruction AFTER the branch instruction. For example:
SEC BCS LABEL NOPA page boundary crossing occurs (i.e. the BCS takes 4 cycles) when (the address of) LABEL and the NOP are on different pages. This means that
CLV BVC LABEL LABEL NOPthe BVC instruction will take 3 cycles no matter what address it is located at.
Affects Flags: B
MODE SYNTAX HEX LEN TIM Implied BRK 00ドル 1 7BRK causes a non-maskable interrupt and increments the program counter by one. Therefore an RTI will go to the address of the BRK +2 so that BRK may be used to replace a two-byte instruction for debugging and the subsequent RTI will be correct.
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Immediate CMP #44ドル $C9 2 2 Zero Page CMP 44ドル $C5 2 3 Zero Page,X CMP 44,ドルX $D5 2 4 Absolute CMP 4400ドル $CD 3 4 Absolute,X CMP 4400,ドルX $DD 3 4+ Absolute,Y CMP 4400,ドルY $D9 3 4+ Indirect,X CMP (44,ドルX) $C1 2 6 Indirect,Y CMP (44ドル),Y $D1 2 5+ + add 1 cycle if page boundary crossedCompare sets flags as if a subtraction had been carried out. If the value in the accumulator is equal or greater than the compared value, the Carry will be set. The equal (Z) and negative (N) flags will be set based on equality or lack thereof and the sign (i.e. A>=80ドル) of the accumulator.
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Immediate CPX #44ドル $E0 2 2 Zero Page CPX 44ドル $E4 2 3 Absolute CPX 4400ドル $EC 3 4Operation and flag results are identical to equivalent mode accumulator CMP ops.
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Immediate CPY #44ドル $C0 2 2 Zero Page CPY 44ドル $C4 2 3 Absolute CPY 4400ドル $CC 3 4Operation and flag results are identical to equivalent mode accumulator CMP ops.
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Zero Page DEC 44ドル $C6 2 5 Zero Page,X DEC 44,ドルX $D6 2 6 Absolute DEC 4400ドル $CE 3 6 Absolute,X DEC 4400,ドルX $DE 3 7
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate EOR #44ドル 49ドル 2 2 Zero Page EOR 44ドル 45ドル 2 3 Zero Page,X EOR 44,ドルX 55ドル 2 4 Absolute EOR 4400ドル 4ドルD 3 4 Absolute,X EOR 4400,ドルX 5ドルD 3 4+ Absolute,Y EOR 4400,ドルY 59ドル 3 4+ Indirect,X EOR (44,ドルX) 41ドル 2 6 Indirect,Y EOR (44ドル),Y 51ドル 2 5+ + add 1 cycle if page boundary crossed
Affect Flags: as noted
These instructions are implied mode, have a length of one byte and require two machine cycles.
MNEMONIC HEX CLC (CLear Carry) 18ドル SEC (SEt Carry) 38ドル CLI (CLear Interrupt) 58ドル SEI (SEt Interrupt) 78ドル CLV (CLear oVerflow) $B8 CLD (CLear Decimal) $D8 SED (SEt Decimal) $F8Notes:
The Interrupt flag is used to prevent (SEI) or enable (CLI) maskable interrupts (aka IRQ's). It does not signal the presence or absence of an interrupt condition. The 6502 will set this flag automatically in response to an interrupt and restore it to its prior status on completion of the interrupt service routine. If you want your interrupt service routine to permit other maskable interrupts, you must clear the I flag in your code.
The Decimal flag controls how the 6502 adds and subtracts. If set, arithmetic is carried out in packed binary coded decimal. This flag is unchanged by interrupts and is unknown on power-up. The implication is that a CLD should be included in boot or interrupt coding.
The Overflow flag is generally misunderstood and therefore under-utilised. After an ADC or SBC instruction, the overflow flag will be set if the twos complement result is less than -128 or greater than +127, and it will cleared otherwise. In twos complement, 80ドル through $FF represents -128 through -1, and 00ドル through 7ドルF represents 0 through +127. Thus, after:
CLC LDA #7ドルF ; +127 ADC #01ドル ; + +1the overflow flag is 1 (+127 + +1 = +128), and after:
CLC LDA #81ドル ; -127 ADC #$FF ; + -1the overflow flag is 0 (-127 + -1 = -128). The overflow flag is not affected by increments, decrements, shifts and logical operations i.e. only ADC, BIT, CLV, PLP, RTI and SBC affect it. There is no op code to set the overflow but a BIT test on an RTS instruction will do the trick.
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Zero Page INC 44ドル $E6 2 5 Zero Page,X INC 44,ドルX $F6 2 6 Absolute INC 4400ドル $EE 3 6 Absolute,X INC 4400,ドルX $FE 3 7
Affects Flags: none
MODE SYNTAX HEX LEN TIM Absolute JMP 5597ドル 4ドルC 3 3 Indirect JMP (5597ドル) 6ドルC 3 5JMP transfers program execution to the following address (absolute) or to the location contained in the following address (indirect). Note that there is no carry associated with the indirect jump so:
AN INDIRECT JUMP MUST NEVER USE A VECTOR BEGINNING ON THE LAST BYTE OF A PAGEFor example if address 3000ドル contains 40,ドル 30ドルFF contains 80,ドル and 3100ドル contains 50,ドル the result of JMP (30ドルFF) will be a transfer of control to 4080ドル rather than 5080ドル as you intended i.e. the 6502 took the low byte of the address from 30ドルFF and the high byte from 3000ドル.
Affects Flags: none
MODE SYNTAX HEX LEN TIM Absolute JSR 5597ドル 20ドル 3 6JSR pushes the address-1 of the next operation on to the stack before transferring program control to the following address. Subroutines are normally terminated by a RTS op code.
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate LDA #44ドル $A9 2 2 Zero Page LDA 44ドル $A5 2 3 Zero Page,X LDA 44,ドルX $B5 2 4 Absolute LDA 4400ドル $AD 3 4 Absolute,X LDA 4400,ドルX $BD 3 4+ Absolute,Y LDA 4400,ドルY $B9 3 4+ Indirect,X LDA (44,ドルX) $A1 2 6 Indirect,Y LDA (44ドル),Y $B1 2 5+ + add 1 cycle if page boundary crossed
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate LDX #44ドル $A2 2 2 Zero Page LDX 44ドル $A6 2 3 Zero Page,Y LDX 44,ドルY $B6 2 4 Absolute LDX 4400ドル $AE 3 4 Absolute,Y LDX 4400,ドルY $BE 3 4+ + add 1 cycle if page boundary crossed
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate LDY #44ドル $A0 2 2 Zero Page LDY 44ドル $A4 2 3 Zero Page,X LDY 44,ドルX $B4 2 4 Absolute LDY 4400ドル $AC 3 4 Absolute,X LDY 4400,ドルX $BC 3 4+ + add 1 cycle if page boundary crossed
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Accumulator LSR A 4ドルA 1 2 Zero Page LSR 44ドル 46ドル 2 5 Zero Page,X LSR 44,ドルX 56ドル 2 6 Absolute LSR 4400ドル 4ドルE 3 6 Absolute,X LSR 4400,ドルX 5ドルE 3 7LSR shifts all bits right one position. 0 is shifted into bit 7 and the original bit 0 is shifted into the Carry.
Use caution with indexed zero page operations as they are subject to wrap-around. For example, if the X register holds $FF and you execute LDA 80,ドルX you will not access 017ドルF as you might expect; instead you access 7ドルF i.e. 80ドル-1. This characteristic can be used to advantage but make sure your code is well commented.
It is possible, however, to access 017ドルF when X = $FF by using the Absolute,X addressing mode of LDA 80,ドルX. That is, instead of:
LDA 80,ドルX ; ZeroPage,X - the resulting object code is: B5 80which accesses 007ドルF when X=$FF, use:
LDA 0080,ドルX ; Absolute,X - the resulting object code is: BD 80 00which accesses 017ドルF when X = $FF (a at cost of one additional byte and one additional cycle). All of the ZeroPage,X and ZeroPage,Y instructions except STX ZeroPage,Y and STY ZeroPage,X have a corresponding Absolute,X and Absolute,Y instruction. Unfortunately, a lot of 6502 assemblers don't have an easy way to force Absolute addressing, i.e. most will assemble a LDA 0080,ドルX as B5 80. One way to overcome this is to insert the bytes using the .BYTE pseudo-op (on some 6502 assemblers this pseudo-op is called DB or DFB, consult the assembler documentation) as follows:
.BYTE $BD,80,ドル00ドル ; LDA 0080,ドルX (absolute,X addressing mode)The comment is optional, but highly recommended for clarity.
In cases where you are writing code that will be relocated you must consider wrap-around when assigning dummy values for addresses that will be adjusted. Both zero and the semi-standard $FFFF should be avoided for dummy labels. The use of zero or zero page values will result in assembled code with zero page opcodes when you wanted absolute codes. With $FFFF, the problem is in addresses+1 as you wrap around to page 0.
When the 6502 is ready for the next instruction it increments the program counter before fetching the instruction. Once it has the op code, it increments the program counter by the length of the operand, if any. This must be accounted for when calculating branches or when pushing bytes to create a false return address (i.e. jump table addresses are made up of addresses-1 when it is intended to use an RTS rather than a JMP).
The program counter is loaded least signifigant byte first. Therefore the most signifigant byte must be pushed first when creating a false return address.
When calculating branches a forward branch of 6 skips the following 6 bytes so, effectively the program counter points to the address that is 8 bytes beyond the address of the branch opcode; and a backward branch of $FA (256-6) goes to an address 4 bytes before the branch instruction.
Op code execution times are measured in machine cycles; one machine cycle equals one clock cycle. Many instructions require one extra cycle for execution if a page boundary is crossed; these are indicated by a + following the time values shown.
Affects Flags: none
MODE SYNTAX HEX LEN TIM Implied NOP $EA 1 2NOP is used to reserve space for future modifications or effectively REM out existing code.
Affects Flags: N Z
MODE SYNTAX HEX LEN TIM Immediate ORA #44ドル 09ドル 2 2 Zero Page ORA 44ドル 05ドル 2 3 Zero Page,X ORA 44,ドルX 15ドル 2 4 Absolute ORA 4400ドル 0ドルD 3 4 Absolute,X ORA 4400,ドルX 1ドルD 3 4+ Absolute,Y ORA 4400,ドルY 19ドル 3 4+ Indirect,X ORA (44,ドルX) 01ドル 2 6 Indirect,Y ORA (44ドル),Y 11ドル 2 5+ + add 1 cycle if page boundary crossed
Affect Flags: N Z
These instructions are implied mode, have a length of one byte and require two machine cycles.
MNEMONIC HEX TAX (Transfer A to X) $AA TXA (Transfer X to A) 8ドルA DEX (DEcrement X) $CA INX (INcrement X) $E8 TAY (Transfer A to Y) $A8 TYA (Transfer Y to A) 98ドル DEY (DEcrement Y) 88ドル INY (INcrement Y) $C8
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Accumulator ROL A 2ドルA 1 2 Zero Page ROL 44ドル 26ドル 2 5 Zero Page,X ROL 44,ドルX 36ドル 2 6 Absolute ROL 4400ドル 2ドルE 3 6 Absolute,X ROL 4400,ドルX 3ドルE 3 7ROL shifts all bits left one position. The Carry is shifted into bit 0 and the original bit 7 is shifted into the Carry.
Affects Flags: N Z C
MODE SYNTAX HEX LEN TIM Accumulator ROR A 6ドルA 1 2 Zero Page ROR 44ドル 66ドル 2 5 Zero Page,X ROR 44,ドルX 76ドル 2 6 Absolute ROR 4400ドル 6ドルE 3 6 Absolute,X ROR 4400,ドルX 7ドルE 3 7ROR shifts all bits right one position. The Carry is shifted into bit 7 and the original bit 0 is shifted into the Carry.
Affects Flags: all
MODE SYNTAX HEX LEN TIM Implied RTI 40ドル 1 6RTI retrieves the Processor Status Word (flags) and the Program Counter from the stack in that order (interrupts push the PC first and then the PSW).
Note that unlike RTS, the return address on the stack is the actual address rather than the address-1.
Affects Flags: none
MODE SYNTAX HEX LEN TIM Implied RTS 60ドル 1 6RTS pulls the top two bytes off the stack (low byte first) and transfers program control to that address+1. It is used, as expected, to exit a subroutine invoked via JSR which pushed the address-1.
RTS is frequently used to implement a jump table where addresses-1 are pushed onto the stack and accessed via RTS eg. to access the second of four routines:
LDX #1 JSR EXEC JMP SOMEWHERE LOBYTE .BYTE <ROUTINE0-1,<ROUTINE1-1 .BYTE <ROUTINE2-1,<ROUTINE3-1 HIBYTE .BYTE >ROUTINE0-1,>ROUTINE1-1 .BYTE >ROUTINE2-1,>ROUTINE3-1 EXEC LDA HIBYTE,X PHA LDA LOBYTE,X PHA RTS
Affects Flags: N V Z C
MODE SYNTAX HEX LEN TIM Immediate SBC #44ドル $E9 2 2 Zero Page SBC 44ドル $E5 2 3 Zero Page,X SBC 44,ドルX $F5 2 4 Absolute SBC 4400ドル $ED 3 4 Absolute,X SBC 4400,ドルX $FD 3 4+ Absolute,Y SBC 4400,ドルY $F9 3 4+ Indirect,X SBC (44,ドルX) $E1 2 6 Indirect,Y SBC (44ドル),Y $F1 2 5+ + add 1 cycle if page boundary crossedSBC results are dependant on the setting of the decimal flag. In decimal mode, subtraction is carried out on the assumption that the values involved are packed BCD (Binary Coded Decimal).
There is no way to subtract without the carry which works as an inverse borrow. i.e, to subtract you set the carry before the operation. If the carry is cleared by the operation, it indicates a borrow occurred.
Affects Flags: none
MODE SYNTAX HEX LEN TIM Zero Page STA 44ドル 85ドル 2 3 Zero Page,X STA 44,ドルX 95ドル 2 4 Absolute STA 4400ドル 8ドルD 3 4 Absolute,X STA 4400,ドルX 9ドルD 3 5 Absolute,Y STA 4400,ドルY 99ドル 3 5 Indirect,X STA (44,ドルX) 81ドル 2 6 Indirect,Y STA (44ドル),Y 91ドル 2 6
These instructions are implied mode, have a length of one byte and require machine cycles as indicated. The "PuLl" operations are known as "POP" on most other microprocessors. With the 6502, the stack is always on page one (100ドル-1ドルFF) and works top down.
MNEMONIC HEX TIM TXS (Transfer X to Stack ptr) 9ドルA 2 TSX (Transfer Stack ptr to X) $BA 2 PHA (PusH Accumulator) 48ドル 3 PLA (PuLl Accumulator) 68ドル 4 PHP (PusH Processor status) 08ドル 3 PLP (PuLl Processor status) 28ドル 4
Affects Flags: none
MODE SYNTAX HEX LEN TIM Zero Page STX 44ドル 86ドル 2 3 Zero Page,Y STX 44,ドルY 96ドル 2 4 Absolute STX 4400ドル 8ドルE 3 4
Affects Flags: none
MODE SYNTAX HEX LEN TIM Zero Page STY 44ドル 84ドル 2 3 Zero Page,X STY 44,ドルX 94ドル 2 4 Absolute STY 4400ドル 8ドルC 3 4
Last Updated Oct 17, 2020.