David is a Senior Lecturer in Computing Science at the Computer Laboratory and a Fellow of Corpus Christi College .

David Greaves, PhD, MIET, is a University Senior Lecturer interested in compiler and hardware design. He has considerable industrial experience at the CTO/Chief Scientist level and has led the design of many hardware systems, including semi-custom VLSI design.

DJG Summer 2021 textbook on Amazon: Arm Modern SoC Design ISBN 978-1-911531-36-4 Title Pages (or download PDF free from Arm).

Lecture Notes: System On Chip Design and Modelling (PDF).     BIGGER PDF.

Major Achievements From Past Decades:

Please click: PROTO MEMOIRS.

Current Activities:

• Project spEEDO: Developing a power debug and monitoring API for virtual platforms and real silicon. A continuation of Power estimation from TLM and very-high-level models of computation (VHLS/Prazor). TLM Power 3 Draft User Manual and Download. AMIQ FDL Report..
• Algorithm Specification Language: Can a high-level programming expression of an algorithm be seamlessly annotated with implementation aspects concerning hardware structure (e.g. number of RAMs, ALU to operation mapping and level of parallelism) for SMP, FPGA/ASIC and GPU targets? TNDJG:008: Transactional Design Expression (Bluespec/SAFL/TLM) Using Chisel HDL/HCL.
• Kiwi: Scientific Acceleration on FPGA (using C# and dotnet DSLs): LINK. FPL Talk (Sept 2014). Comp-Arch Talk (May 2011).
• Profiles for compositional formal checking: can metadata for system components be digitally signed according to the class of automated checker and checking overhead required when a system is assembled?
• Multi-blade Co-Synthesis Kiwi-Axelgraph2.

Quote of the day: 'Although there is no accepted taxonomy of high versus low-level languages for hardware design, we can roughly relate a gate-level net list to machine code, RTL to assembly language, hardware construction languages such as Chisel and Lava as low-level languages and anything that makes automatic assignment of work to clock cycles as high-level languages.' --- DJ Greaves.

New PhD Students

I am expecting to take at most one new PhD student a year in the area of special-purpose or unusual compiler tools, especially those generating hardware or parallel implementations of a high-level work description.

Future Activities:

• IP block machine-readable datasheets for incremental HLS and verification: CARDs proposal.
• A new System-Level Description Language (SLDL) for EDA, including the best parts of the H2 temporary language.
• Draft items, yet to be published: LINK.