|
1 | | -/* Modified by Nober <s0913768710@gmail.com> |
2 | | - 13-DEC-2019 - Define all CSR macro |
3 | | -*/ |
4 | | - |
5 | | -/* |
6 | | -RISCV emulator for the RV32I architecture |
7 | | -based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ |
8 | | -stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test |
9 | | -by Frank Buss, 2018 |
10 | | - |
11 | | -Requires libelf-dev: |
12 | | - |
13 | | -sudo apt-get install libelf-dev |
14 | | - |
15 | | - |
16 | | -Compile it like this: |
17 | | - |
18 | | -gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i |
19 | | - |
20 | | - |
21 | | -It is compatible to Spike for the command line arguments, which means you can run |
22 | | -the compliance test from https://github.com/riscv/riscv-compliance like this: |
23 | | - |
24 | | -make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant |
25 | | - |
26 | | -It is also compatible with qemu32, as it is used for Zephyr. You can compile the |
27 | | -Zephyr examples for qemu like this: |
28 | | - |
29 | | -cd zephyr |
30 | | -source zephyr-env.sh |
31 | | -cd samples/synchronization |
32 | | -mkdir build && cd build |
33 | | -cmake -GNinja -DBOARD=qemu_riscv32 .. |
34 | | -ninja |
35 | | - |
36 | | -After this you can run it with the emulator like this: |
37 | | - |
38 | | -emu-rv32i zephyr/zephyr.elf |
39 | | - |
| 1 | +#include <stdint.h> |
40 | 2 |
|
41 | | -original copyright: |
42 | | -*/ |
| 3 | +// ====================================================== // |
| 4 | +// =================== User Trap Setup ================== // |
| 5 | +// ====================================================== // |
| 6 | +uint32_t ustatus; /* User status register */ |
| 7 | +uint32_t uie; /* User interrupt-enable register */ |
| 8 | +uint32_t utvec; /* User trap handler base address */ |
| 9 | +// ====================================================== // |
| 10 | +// ================= User Trap Handling ================= // |
| 11 | +// ====================================================== // |
| 12 | +uint32_t uscratch; /* Scratch register for user trap handlers*/ |
| 13 | +uint32_t uepc; /* User exception program counter */ |
| 14 | +uint32_t ucause; /* User trap cause*/ |
| 15 | +uint32_t ubadaddr; /* User bad address */ |
| 16 | +uint32_t uip; /* User interrupt pending */ |
| 17 | +// ====================================================== // |
| 18 | +// ============== User Floating-Point CSRs ============== // |
| 19 | +// ====================================================== // |
| 20 | +uint32_t fflags; /* Floating-Point Accrued Exceptions*/ |
| 21 | +uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ |
| 22 | +uint32_t fcsr; /* Floating-Point Control and Status Register (frm + fflags )*/ |
| 23 | +// ====================================================== // |
| 24 | +// ================ User Counter / TImers =============== // |
| 25 | +// ====================================================== // |
| 26 | +uint32_t cycle; /* Cycle counter for RDCYCLE instruction */ |
| 27 | +uint32_t time; /* Timer for RDTIME instruction */ |
| 28 | +uint32_t instret; /* Instructions-retired counter for RDINSTRET instructions*/ |
| 29 | +uint32_t cycleh; /* Upper 32 bits of cycle, RV32I only. */ |
| 30 | +uint32_t timeh; /* Upper 32 bits of time, RV32I only. */ |
43 | 31 |
|
44 | 32 |
|
| 33 | +// ====================================================== // |
| 34 | +// ================ Supervior Trap Setup ================ // |
| 35 | +// ====================================================== // |
| 36 | +uint32_t sstatus; /* Supervisor status register */ |
| 37 | +uint32_t sedeleg; /* Supervisor exception delegation register */ |
| 38 | +uint32_t sideleg; /* Supervisor interrupt delegation register */ |
| 39 | +uint32_t sie; /* Supervisor interrupt-enable register*/ |
| 40 | +uint32_t stvec; /* Supervisor trap handler base address */ |
| 41 | +// ====================================================== // |
| 42 | +// ============== Supervisor Trap Handling ============== // |
| 43 | +// ====================================================== // |
| 44 | +uint32_t sscratch; /* Scratch register for supervisor trap handlers */ |
| 45 | +uint32_t sepc; /* Supervisor exception program counter */ |
| 46 | +uint32_t scause; /* Supervisor trap cause */ |
| 47 | +uint32_t sbadaddr; /* Supervisor bad address */ |
| 48 | +uint32_t sip; /* Supervisor interrupt pending */ |
| 49 | +// ====================================================== // |
| 50 | +// ======== Supervisor Protection and Translation ======= // |
| 51 | +// ====================================================== // |
| 52 | +uint32_t sptbr; /* Page-table base register */ |
45 | 53 |
|
46 | | -/* |
47 | | - * RISCV emulator |
48 | | - * |
49 | | - * Copyright (c) 2016 Fabrice Bellard |
50 | | - * |
51 | | - * Permission is hereby granted, free of charge, to any person obtaining a copy |
52 | | - * of this software and associated documentation files (the "Software"), to deal |
53 | | - * in the Software without restriction, including without limitation the rights |
54 | | - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
55 | | - * copies of the Software, and to permit persons to whom the Software is |
56 | | - * furnished to do so, subject to the following conditions: |
57 | | - * |
58 | | - * The above copyright notice and this permission notice shall be included in |
59 | | - * all copies or substantial portions of the Software. |
60 | | - * |
61 | | - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
62 | | - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
63 | | - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
64 | | - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
65 | | - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
66 | | - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
67 | | - * THE SOFTWARE. |
68 | | - */ |
69 | 54 |
|
70 | | -#include <stdint.h> |
| 55 | +// ====================================================== // |
| 56 | +// ================ Hypervisor Trap Setup =============== // |
| 57 | +// ====================================================== // |
| 58 | +uint32_t hstatus; /* Hypervisor status register */ |
| 59 | +uint32_t hedeleg; /* Hypervisor exception delegation register */ |
| 60 | +uint32_t hideleg; /* Hyperbisor interrupt delegation register */ |
| 61 | +uint32_t hie; /* Hypervisor interrupt-enable register */ |
| 62 | +uint32_t htvec; /* Hypervisor trap handler base address */ |
| 63 | +// ====================================================== // |
| 64 | +// ============== Hypervisor Trap Handling ============== // |
| 65 | +// ====================================================== // |
| 66 | +uint32_t hscratch; /* Scratch register for hypervisor trap handlers */ |
| 67 | +uint32_t hepc; /* Hypervisor exception program counter */ |
| 68 | +uint32_t hcause; /* Hypervisor trap cause */ |
| 69 | +uint32_t hbadaddr; /* Hypervisor bad address */ |
| 70 | +uint32_t hip; /* Hypervisor interrupt pending */ |
| 71 | +// ====================================================== // |
| 72 | +// ======== Hypervisor Protection and Translation ======= // |
| 73 | +// ====================================================== // |
| 74 | +// uint32_t TBD; /* TBD */ |
71 | 75 |
|
72 | 76 |
|
73 | 77 | // ====================================================== // |
74 | | -// =================== User Trap Setup ================== // |
| 78 | +// ============ Machine Information Register ============ // |
75 | 79 | // ====================================================== // |
76 | | -uint32_t ustatus; /* User status register */ |
77 | | -uint32_t uie; /* User interrupt-enable register */ |
78 | | -uint32_t utvec; /* User trap handler base address */ |
| 80 | +uint32_t mvendorid; /* Vendor ID*/ |
| 81 | +uint32_t marchid; /* Architecture ID */ |
| 82 | +uint32_t mimpid; /* Implementation ID */ |
| 83 | +uint32_t mhartid; /* Hardware thread ID */ |
79 | 84 | // ====================================================== // |
80 | | -// ================= User Trap Handling ================= // |
| 85 | +// ================= Machine Trap Setup ================= // |
81 | 86 | // ====================================================== // |
82 | | -uint32_t uscratch; /* Scratch register for user trap handlers*/ |
83 | | -uint32_t uepc; /* User exception program counter */ |
84 | | -uint32_t ucause; /* User trap cause*/ |
85 | | -uint32_t ubadaddr; /* User bad address */ |
86 | | -uint32_t uip; /* User interrupt pending */ |
| 87 | +uint32_t mstatus; /* Machine status register */ |
| 88 | +uint32_t misa; /* ISA and extensions */ |
| 89 | +uint32_t medeleg; /* Machine exception delegation register */ |
| 90 | +uint32_t mideleg; /* Machine interrupt delegation register */ |
| 91 | +uint32_t mie; /* Machine interrupt-enable register */ |
| 92 | +uint32_t mtvec; /* Machine trap-handler base address */ |
87 | 93 | // ====================================================== // |
88 | | -// ============== User Floating-Point CSRs ============== // |
| 94 | +// ================ Machine Trap Handling =============== // |
| 95 | +// ====================================================== // |
| 96 | +uint32_t mscratch; /* Scratch register for machine trap handlers */ |
| 97 | +uint32_t mepc; /* Machine exception program counter */ |
| 98 | +uint32_t mcause; /* Machine trap cause */ |
| 99 | +uint32_t mbadaddr; /* Machine bad address */ |
| 100 | +uint32_t mip; /* Machine interrupt pending */ |
| 101 | +// ====================================================== // |
| 102 | +// ========= Machine Protextion and Translation ========= // |
89 | 103 | // ====================================================== // |
90 | | -uint32_t fflags; /* Floating-Point Accrued Exceptions*/ |
91 | | -uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ |
| 104 | +uint32_t mbase; /* Base regsiter */ |
| 105 | +uint32_t mbound; /* Bound register */ |
| 106 | +uint32_t mibase; /* Instruction base register */ |
| 107 | +uint32_t mibound; /* Instruction bound register */ |
| 108 | +uint32_t mdbase; /* Data base register */ |
| 109 | +uint32_t mdbound; /* Data bound register */ |
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