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Commit 2392b2d

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Solve 2024 day 24 part 1
1 parent 1580750 commit 2392b2d

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3 files changed

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3 files changed

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x00: 1
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x01: 1
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x02: 0
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x03: 0
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x04: 0
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x05: 1
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x06: 0
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x07: 1
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x08: 1
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x09: 0
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x10: 1
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x11: 0
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x12: 0
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x13: 0
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x14: 1
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x15: 1
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x16: 1
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x17: 0
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x18: 0
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x19: 0
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x20: 1
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x21: 0
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x22: 1
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x23: 0
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x24: 0
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x25: 0
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x26: 0
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x27: 1
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x28: 0
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x29: 1
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x30: 0
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x31: 0
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x32: 1
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x33: 1
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x34: 1
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x35: 0
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x36: 0
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x37: 0
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x38: 1
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x39: 1
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x40: 1
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x41: 1
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x42: 0
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x43: 0
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x44: 1
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y00: 1
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y01: 0
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y02: 1
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y03: 1
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y04: 0
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y05: 0
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y06: 1
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y07: 1
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y08: 0
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y09: 1
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y10: 1
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y11: 1
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y12: 1
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y13: 0
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y14: 1
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y15: 0
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y16: 0
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y17: 1
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y18: 0
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y19: 1
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y20: 0
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y21: 1
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y22: 1
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y23: 1
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y24: 0
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y25: 1
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y26: 1
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y27: 0
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y28: 1
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y29: 1
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y30: 0
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y31: 1
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y32: 0
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y33: 0
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y34: 0
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y35: 1
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y36: 1
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y37: 1
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y38: 1
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y39: 1
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y40: 0
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y41: 1
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y42: 0
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y43: 1
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y44: 1
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x23 AND y23 -> mhq
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dbf XOR dsb -> z35
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x41 AND y41 -> qss
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kbv AND ctw -> qhg
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djs OR tgk -> ccp
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nmw AND bgp -> bcr
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jns OR npn -> jbv
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y29 AND x29 -> tjt
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y17 AND x17 -> nhh
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kmm AND ptk -> vnr
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hbr AND qfp -> mjr
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qfk AND pvj -> ndp
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tvb XOR jhd -> z25
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y29 XOR x29 -> wft
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rqd AND cns -> grb
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jbv AND kjg -> vjg
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tvm XOR pkw -> z38
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vwd AND kvv -> mgw
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nmw XOR bgp -> z02
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cdc OR stq -> z21
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x16 XOR y16 -> mft
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x37 XOR y37 -> hbr
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x24 XOR y24 -> cns
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y40 XOR x40 -> pgc
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ccd OR cst -> cbk
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fht XOR ddw -> z20
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wft AND nnq -> stm
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srk AND sjm -> fwg
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y06 AND x06 -> cnm
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gqg XOR pmv -> z07
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ndp OR nfq -> rgv
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bsm OR vsc -> fjn
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x15 XOR y15 -> srk
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bwv XOR vbq -> z42
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kbv XOR ctw -> z31
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x10 XOR y10 -> htc
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x08 XOR y08 -> knh
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fgc AND dvm -> nfn
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y03 AND x03 -> ssj
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x26 XOR y26 -> spf
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y02 AND x02 -> psw
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x36 XOR y36 -> fcf
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ptj OR dtg -> spg
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stm OR tjt -> gsj
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mmw XOR ncf -> z23
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y26 AND x26 -> csh
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rrj AND mft -> tnt
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x05 XOR y05 -> chs
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x16 AND y16 -> khn
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nqm AND fmf -> tgq
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wft XOR nnq -> z29
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y13 AND x13 -> ggg
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rcb OR khg -> mfp
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y28 AND x28 -> wgd
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csf AND bck -> qsg
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x31 XOR y31 -> kbv
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rrj XOR mft -> z16
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hhg AND ccp -> msp
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y00 XOR x00 -> z00
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x25 XOR y25 -> khg
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x42 AND y42 -> djs
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ggg OR hvg -> csf
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pps XOR wdg -> vdc
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y04 XOR x04 -> pvj
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qtg AND knh -> ccd
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x27 AND y27 -> jns
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jdk OR pmr -> spk
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nhm XOR jmr -> z18
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fpk AND dfh -> ccr
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x06 XOR y06 -> bgq
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x38 AND y38 -> dcc
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x22 XOR y22 -> jkq
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vbq AND bwv -> tgk
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x14 XOR y14 -> bck
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fjn AND htc -> dtg
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kfd XOR rtg -> z19
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bvk OR khh -> nmw
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x34 XOR y34 -> ptk
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mmw AND ncf -> rkf
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y11 AND x11 -> rvg
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wgd OR vjg -> nnq
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qss OR wtt -> bwv
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dmb OR crv -> ddw
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y08 AND x08 -> cst
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nhh OR tgq -> jmr
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cpt XOR fqc -> z32
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tnt OR khn -> fmf
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fbk AND tcq -> hvg
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spq XOR gpk -> z01
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x02 XOR y02 -> bgp
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x20 AND y20 -> fct
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x36 AND y36 -> jbq
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x12 AND y12 -> z12
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mfp XOR spf -> z26
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spg XOR hhm -> z11
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y32 AND x32 -> rjq
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y04 AND x04 -> nfq
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pkj OR msp -> kvv
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tvc OR dcc -> dvm
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vnr OR krb -> dbf
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fmf XOR nqm -> z17
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rtg AND kfd -> dmb
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fvh XOR pgc -> z40
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fcf XOR spk -> z36
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pvc OR gst -> kmm
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cbk AND nbm -> vsc
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x09 AND y09 -> bsm
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x07 XOR y07 -> gqg
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ptk XOR kmm -> z34
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x28 XOR y28 -> kjg
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dbm OR jft -> qtg
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jbr AND wcs -> z33
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y42 XOR x42 -> vbq
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y00 AND x00 -> spq
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y19 XOR x19 -> kfd
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tbn OR grb -> jhd
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kvv XOR vwd -> z44
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wcs XOR jbr -> gst
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srk XOR sjm -> z15
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y39 AND x39 -> cbf
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bgq XOR wdh -> z06
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bbn AND rsc -> cdc
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y18 XOR x18 -> nhm
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tvm AND pkw -> tvc
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x23 XOR y23 -> ncf
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x19 AND y19 -> crv
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qhg OR gnc -> fqc
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jbv XOR kjg -> z28
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y05 AND x05 -> nph
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x32 XOR y32 -> cpt
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x31 AND y31 -> gnc
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ccp XOR hhg -> z43
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x15 AND y15 -> gtf
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jmr AND nhm -> ptd
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x10 AND y10 -> ptj
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bgq AND wdh -> dgh
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ftw XOR gsj -> z30
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x44 AND y44 -> bds
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fjn XOR htc -> z10
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y43 AND x43 -> pkj
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y30 AND x30 -> nmj
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tvb AND jhd -> rcb
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x40 AND y40 -> gdm
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mgw OR bds -> z45
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fdv AND dfs -> wtt
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rkf OR mhq -> rqd
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pvj XOR qfk -> z04
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pmv AND gqg -> dbm
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x21 XOR y21 -> bbn
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x38 XOR y38 -> tvm
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mjr OR kpb -> pkw
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jbq OR vmj -> qfp
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jkq XOR nhn -> z22
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qfn OR fct -> rsc
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x30 XOR y30 -> ftw
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y35 XOR x35 -> dsb
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y24 AND x24 -> tbn
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fcf AND spk -> vmj
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cnm OR dgh -> pmv
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x27 XOR y27 -> mcv
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chs XOR rgv -> z05
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vdc OR kcp -> fbk
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y39 XOR x39 -> fgc
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x13 XOR y13 -> tcq
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ssj OR ccr -> qfk
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fwg OR gtf -> rrj
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knh XOR qtg -> z08
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fqc AND cpt -> nfh
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y17 XOR x17 -> nqm
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hbr XOR qfp -> z37
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y22 AND x22 -> nrq
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y01 XOR x01 -> gpk
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jhv OR nph -> wdh
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dfs XOR fdv -> z41
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gqb OR csh -> mbp
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dvm XOR fgc -> z39
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y03 XOR x03 -> fpk
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mfp AND spf -> gqb
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x44 XOR y44 -> vwd
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gpk AND spq -> bvk
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x21 AND y21 -> stq
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cbf OR nfn -> fvh
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spg AND hhm -> wvv
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cns XOR rqd -> z24
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rjq OR nfh -> wcs
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mcv AND mbp -> npn
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wdg AND pps -> kcp
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nrq OR vkg -> mmw
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x33 AND y33 -> pvc
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x20 XOR y20 -> fht
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y43 XOR x43 -> hhg
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dfh XOR fpk -> z03
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fbk XOR tcq -> z13
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x09 XOR y09 -> nbm
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pwp OR nmj -> ctw
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y25 AND x25 -> tvb
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y34 AND x34 -> krb
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x11 XOR y11 -> hhm
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hdq OR gdm -> fdv
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mcv XOR mbp -> z27
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nbm XOR cbk -> z09
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fvh AND pgc -> hdq
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jkq AND nhn -> vkg
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dwt OR qsg -> sjm
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dbf AND dsb -> pmr
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rsc XOR bbn -> nhn
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y14 AND x14 -> dwt
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x35 AND y35 -> jdk
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x41 XOR y41 -> dfs
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y37 AND x37 -> kpb
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bck XOR csf -> z14
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y07 AND x07 -> jft
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sdp OR ptd -> rtg
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y01 AND x01 -> khh
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bcr OR psw -> dfh
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chs AND rgv -> jhv
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y18 AND x18 -> sdp
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ddw AND fht -> qfn
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x33 XOR y33 -> jbr
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gsj AND ftw -> pwp
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x12 XOR y12 -> pps
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rvg OR wvv -> wdg
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package eu.sim642.adventofcode2024
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import scala.collection.mutable
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object Day24 {
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enum Op {
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case And
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case Or
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case Xor
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}
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enum Wire {
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case Input(value: Boolean)
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case Gate(lhs: String, op: Op, rhs: String)
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}
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type Circuit = Map[String, Wire]
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def getZValue(circuit: Circuit): Long = {
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val memo = mutable.Map.empty[String, Boolean]
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def evalName(name: String): Boolean =
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memo.getOrElseUpdate(name, evalWire(circuit(name)))
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def evalWire(wire: Wire): Boolean = wire match {
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case Wire.Input(value) => value
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case Wire.Gate(lhs, op, rhs) =>
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val left = evalName(lhs)
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val right = evalName(rhs)
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op match {
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case Op.And => left && right
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case Op.Or => left || right
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case Op.Xor => left != right
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}
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}
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circuit.keys
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.filter(_.startsWith("z"))
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.toSeq
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.sorted
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.foldRight(0L)({ case (zName, acc) =>
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acc << 1 | (if (evalName(zName)) 1 else 0)
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})
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}
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def parseInput(s: String): (String, Wire.Input) = s match {
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case s"$name: 0" => name -> Wire.Input(false)
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case s"$name: 1" => name -> Wire.Input(true)
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}
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def parseGate(s: String): (String, Wire.Gate) = s match {
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case s"$lhs AND $rhs -> $name" => name ->Wire.Gate(lhs, Op.And, rhs)
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case s"$lhs OR $rhs -> $name" => name -> Wire.Gate(lhs, Op.Or, rhs)
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case s"$lhs XOR $rhs -> $name" => name -> Wire.Gate(lhs, Op.Xor, rhs)
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}
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def parseCircuit(input: String): Circuit = input match {
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case s"$inputs\n\n$gates" =>
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val inputMap = inputs.linesIterator.map(parseInput).toMap
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val gateMap = gates.linesIterator.map(parseGate).toMap
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inputMap ++ gateMap
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}
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lazy val input: String = scala.io.Source.fromInputStream(getClass.getResourceAsStream("day24.txt")).mkString.trim
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def main(args: Array[String]): Unit = {
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println(getZValue(parseCircuit(input)))
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}
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}

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