Commit 1aebf67

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clippy: allow some future lints (from clippy::nursery)

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Lines changed: 1 addition & 0 deletions

Original file line number	Diff line number	Diff line change
`@@ -107,6 +107,7 @@ pub struct AtaDevice<'a> {`
`107`	`107`	`}`
`108`	`108`
`109`	`109`	`impl AtaDevice<'_> {`
	`110`	`+ #[allow(clippy::needless_pass_by_ref_mut)] // cast to mutable ptr`
`110`	`111`	`const fn proto_mut(&mut self) -> *mut AtaPassThruProtocol {`
`111`	`112`	`ptr::from_ref(self.proto).cast_mut()`
`112`	`113`	`}`

Lines changed: 1 addition & 0 deletions

Original file line number	Diff line number	Diff line change
`@@ -121,6 +121,7 @@ pub struct NvmeNamespace<'a> {`
`121`	`121`	`}`
`122`	`122`
`123`	`123`	`impl NvmeNamespace<'_> {`
	`124`	`+ #[allow(clippy::needless_pass_by_ref_mut)] // cast to mutable ptr`
`124`	`125`	`const fn proto_mut(&mut self) -> *mut NvmExpressPassThruProtocol {`
`125`	`126`	`ptr::from_ref(self.proto).cast_mut()`
`126`	`127`	`}`

Lines changed: 1 addition & 0 deletions

Original file line number	Diff line number	Diff line change
`@@ -131,6 +131,7 @@ mod tests {`
`131`	`131`	`use super::PciIoAddress;`
`132`	`132`
`133`	`133`	`#[test]`
	`134`	`+ #[allow(clippy::unusual_byte_groupings)]`
`134`	`135`	`fn test_pci_ioaddr_raw_conversion() {`
`135`	`136`	`assert_eq!(size_of::<u64>(), size_of::<PciIoAddress>());`
`136`	`137`	`let srcaddr = PciIoAddress {`

Lines changed: 1 addition & 0 deletions

Original file line number	Diff line number	Diff line change
`@@ -130,6 +130,7 @@ pub struct ScsiDevice<'a> {`
`130`	`130`	`target_lun: ScsiTargetLun,`
`131`	`131`	`}`
`132`	`132`	`impl ScsiDevice<'_> {`
	`133`	`+ #[allow(clippy::needless_pass_by_ref_mut)] // cast to mutable ptr`
`133`	`134`	`const fn proto_mut(&mut self) -> *mut ExtScsiPassThruProtocol {`
`134`	`135`	`ptr::from_ref(self.proto).cast_mut()`
`135`	`136`	`}`

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