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Commit cbf0987

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Auto merge of #144204 - fee1-dead-contrib:rollup-56951om, r=fee1-dead
Rollup of 12 pull requests Successful merges: - #141260 (Allow volatile access to non-Rust memory, including address 0) - #143604 (Stabilize `const_float_round_methods`) - #143833 (Ban projecting into SIMD types [MCP838]) - #143988 ([rustdoc] Make aliases search support partial matching) - #144078 (Fix debuginfo-lto-alloc.rs test) - #144111 (Remove deprecated `MaybeUninit` slice methods) - #144116 (Fixes for LLVM 21) - #144134 (Cleanup unicode table gen) - #144142 (Add implicit sized bound to trait ascription types) - #144148 (Remove pretty print hack for async blocks) - #144169 (interpret: fix TypeId pointers being considered data pointers) - #144196 (Initialize mingw for the runner's user) r? `@ghost` `@rustbot` modify labels: rollup
2 parents 6707bf0 + a793976 commit cbf0987

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‎.github/workflows/ci.yml

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -182,11 +182,6 @@ jobs:
182182
- name: install MinGW
183183
run: src/ci/scripts/install-mingw.sh
184184

185-
# Workaround for spurious ci failures after mingw install
186-
# see https://rust-lang.zulipchat.com/#narrow/channel/242791-t-infra/topic/Spurious.20bors.20CI.20failures/near/528915775
187-
- name: ensure home dir exists
188-
run: mkdir -p ~
189-
190185
- name: install ninja
191186
run: src/ci/scripts/install-ninja.sh
192187

‎compiler/rustc_codegen_cranelift/example/float-minmax-pass.rs

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,12 @@
1111
#[derive(Copy, Clone, PartialEq, Debug)]
1212
struct f32x4(pub [f32; 4]);
1313

14+
impl f32x4 {
15+
fn into_array(self) -> [f32; 4] {
16+
unsafe { std::mem::transmute(self) }
17+
}
18+
}
19+
1420
use std::intrinsics::simd::*;
1521

1622
fn main() {
@@ -29,22 +35,22 @@ fn main() {
2935
unsafe {
3036
let min0 = simd_fmin(x, y);
3137
let min1 = simd_fmin(y, x);
32-
assert_eq!(min0, min1);
38+
assert_eq!(min0.into_array(), min1.into_array());
3339
let e = f32x4([1.0, 1.0, 3.0, 3.0]);
34-
assert_eq!(min0, e);
40+
assert_eq!(min0.into_array(), e.into_array());
3541
let minn = simd_fmin(x, n);
36-
assert_eq!(minn, x);
42+
assert_eq!(minn.into_array(), x.into_array());
3743
let minn = simd_fmin(y, n);
38-
assert_eq!(minn, y);
44+
assert_eq!(minn.into_array(), y.into_array());
3945

4046
let max0 = simd_fmax(x, y);
4147
let max1 = simd_fmax(y, x);
42-
assert_eq!(max0, max1);
48+
assert_eq!(max0.into_array(), max1.into_array());
4349
let e = f32x4([2.0, 2.0, 4.0, 4.0]);
44-
assert_eq!(max0, e);
50+
assert_eq!(max0.into_array(), e.into_array());
4551
let maxn = simd_fmax(x, n);
46-
assert_eq!(maxn, x);
52+
assert_eq!(maxn.into_array(), x.into_array());
4753
let maxn = simd_fmax(y, n);
48-
assert_eq!(maxn, y);
54+
assert_eq!(maxn.into_array(), y.into_array());
4955
}
5056
}

‎compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,7 +348,8 @@ fn main() {
348348
struct V([f64; 2]);
349349

350350
let f = V([0.0, 1.0]);
351-
let _a = f.0[0];
351+
let fp = (&raw const f) as *const [f64; 2];
352+
let _a = (unsafe { &*fp })[0];
352353

353354
stack_val_align();
354355
}

‎compiler/rustc_codegen_llvm/src/back/owned_target_machine.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ impl OwnedTargetMachine {
3939
debug_info_compression: &CStr,
4040
use_emulated_tls: bool,
4141
args_cstr_buff: &[u8],
42+
use_wasm_eh: bool,
4243
) -> Result<Self, LlvmError<'static>> {
4344
assert!(args_cstr_buff.len() > 0);
4445
assert!(
@@ -72,6 +73,7 @@ impl OwnedTargetMachine {
7273
use_emulated_tls,
7374
args_cstr_buff.as_ptr() as *const c_char,
7475
args_cstr_buff.len(),
76+
use_wasm_eh,
7577
)
7678
};
7779

‎compiler/rustc_codegen_llvm/src/back/write.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ use rustc_codegen_ssa::back::write::{
1515
BitcodeSection, CodegenContext, EmitObj, ModuleConfig, TargetMachineFactoryConfig,
1616
TargetMachineFactoryFn,
1717
};
18+
use rustc_codegen_ssa::base::wants_wasm_eh;
1819
use rustc_codegen_ssa::traits::*;
1920
use rustc_codegen_ssa::{CompiledModule, ModuleCodegen, ModuleKind};
2021
use rustc_data_structures::profiling::SelfProfilerRef;
@@ -285,6 +286,8 @@ pub(crate) fn target_machine_factory(
285286
let file_name_display_preference =
286287
sess.filename_display_preference(RemapPathScopeComponents::DEBUGINFO);
287288

289+
let use_wasm_eh = wants_wasm_eh(sess);
290+
288291
Arc::new(move |config: TargetMachineFactoryConfig| {
289292
let path_to_cstring_helper = |path: Option<PathBuf>| -> CString {
290293
let path = path.unwrap_or_default();
@@ -321,6 +324,7 @@ pub(crate) fn target_machine_factory(
321324
&debuginfo_compression,
322325
use_emulated_tls,
323326
&args_cstr_buff,
327+
use_wasm_eh,
324328
)
325329
})
326330
}

‎compiler/rustc_codegen_llvm/src/context.rs

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,11 @@ pub(crate) unsafe fn create_module<'ll>(
207207
// LLVM 21 updated the default layout on nvptx: https://github.com/llvm/llvm-project/pull/124961
208208
target_data_layout = target_data_layout.replace("e-p6:32:32-i64", "e-i64");
209209
}
210+
if sess.target.arch == "amdgpu" {
211+
// LLVM 21 adds the address width for address space 8.
212+
// See https://github.com/llvm/llvm-project/pull/139419
213+
target_data_layout = target_data_layout.replace("p8:128:128:128:48", "p8:128:128")
214+
}
210215
}
211216

212217
// Ensure the data-layout values hardcoded remain the defaults.

‎compiler/rustc_codegen_llvm/src/llvm/ffi.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2425,6 +2425,7 @@ unsafe extern "C" {
24252425
UseEmulatedTls: bool,
24262426
ArgsCstrBuff: *const c_char,
24272427
ArgsCstrBuffLen: usize,
2428+
UseWasmEH: bool,
24282429
) -> *mut TargetMachine;
24292430

24302431
pub(crate) fn LLVMRustDisposeTargetMachine(T: *mut TargetMachine);

‎compiler/rustc_codegen_ssa/src/mir/operand.rs

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -329,20 +329,11 @@ impl<'a, 'tcx, V: CodegenObject> OperandRef<'tcx, V> {
329329
let offset = self.layout.fields.offset(i);
330330

331331
if !bx.is_backend_ref(self.layout) && bx.is_backend_ref(field) {
332-
if let BackendRepr::SimdVector { count, .. } = self.layout.backend_repr
333-
&& let BackendRepr::Memory { sized: true } = field.backend_repr
334-
&& count.is_power_of_two()
335-
{
336-
assert_eq!(field.size, self.layout.size);
337-
// This is being deprecated, but for now stdarch still needs it for
338-
// Newtype vector of array, e.g. #[repr(simd)] struct S([i32; 4]);
339-
let place = PlaceRef::alloca(bx, field);
340-
self.val.store(bx, place.val.with_type(self.layout));
341-
return bx.load_operand(place);
342-
} else {
343-
// Part of https://github.com/rust-lang/compiler-team/issues/838
344-
bug!("Non-ref type {self:?} cannot project to ref field type {field:?}");
345-
}
332+
// Part of https://github.com/rust-lang/compiler-team/issues/838
333+
span_bug!(
334+
fx.mir.span,
335+
"Non-ref type {self:?} cannot project to ref field type {field:?}",
336+
);
346337
}
347338

348339
let val = if field.is_zst() {

‎compiler/rustc_const_eval/src/interpret/memory.rs

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ pub enum AllocKind {
6767
LiveData,
6868
/// A function allocation (that fn ptrs point to).
6969
Function,
70-
/// A (symbolic) vtable allocation.
71-
VTable,
70+
/// A "virtual" allocation, used for vtables and TypeId.
71+
Virtual,
7272
/// A dead allocation.
7373
Dead,
7474
}
@@ -950,11 +950,9 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
950950
let (size, align) = global_alloc.size_and_align(*self.tcx, self.typing_env);
951951
let mutbl = global_alloc.mutability(*self.tcx, self.typing_env);
952952
let kind = match global_alloc {
953-
GlobalAlloc::TypeId { .. }
954-
| GlobalAlloc::Static { .. }
955-
| GlobalAlloc::Memory { .. } => AllocKind::LiveData,
953+
GlobalAlloc::Static { .. } | GlobalAlloc::Memory { .. } => AllocKind::LiveData,
956954
GlobalAlloc::Function { .. } => bug!("We already checked function pointers above"),
957-
GlobalAlloc::VTable { .. } => AllocKind::VTable,
955+
GlobalAlloc::VTable { .. } | GlobalAlloc::TypeId{ .. }=> AllocKind::Virtual,
958956
};
959957
return AllocInfo::new(size, align, kind, mutbl);
960958
}

‎compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2495,6 +2495,14 @@ impl<'tcx> dyn HirTyLowerer<'tcx> + '_ {
24952495
ty::List::empty(),
24962496
PredicateFilter::All,
24972497
);
2498+
self.add_sizedness_bounds(
2499+
&mut bounds,
2500+
self_ty,
2501+
hir_bounds,
2502+
None,
2503+
None,
2504+
hir_ty.span,
2505+
);
24982506
self.register_trait_ascription_bounds(bounds, hir_ty.hir_id, hir_ty.span);
24992507
self_ty
25002508
}

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