Commit a3a0e90

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Rollup merge of #146134 - maurer:nvptx-sync, r=durin42

llvm: nvptx: Layout update to match LLVM LLVM upstream switched layouts to support 256-bit vector load/store. `@rustbot` label llvm-main r? durin42

2 parents ebbefbe + 5d9f8fc commit a3a0e90Copy full SHA for a3a0e90

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compiler
- rustc_codegen_llvm/src
  - context.rs
- rustc_target/src/spec/targets
  - nvptx64_nvidia_cuda.rs

-1

lines changed

Lines changed: 4 additions & 0 deletions

Original file line number	Diff line number	Diff line change
`@@ -217,6 +217,10 @@ pub(crate) unsafe fn create_module<'ll>(`
`217`	`217`	`// LLVM 22.0 updated the default layout on avr: https://github.com/llvm/llvm-project/pull/153010`
`218`	`218`	`target_data_layout = target_data_layout.replace("n8:16", "n8")`
`219`	`219`	`}`
	`220`	`+ if sess.target.arch == "nvptx64" {`
	`221`	`+ // LLVM 22 updated the NVPTX layout to indicate 256-bit vector load/store: https://github.com/llvm/llvm-project/pull/155198`
	`222`	`+ target_data_layout = target_data_layout.replace("-i256:256", "");`
	`223`	`+ }`
`220`	`224`	`}`
`221`	`225`
`222`	`226`	`// Ensure the data-layout values hardcoded remain the defaults.`

Lines changed: 1 addition & 1 deletion

Original file line number	Diff line number	Diff line change
`@@ -6,7 +6,7 @@ use crate::spec::{`
`6`	`6`	`pub(crate) fn target() -> Target {`
`7`	`7`	`Target {`
`8`	`8`	`arch: "nvptx64".into(),`
`9`		`- data_layout: "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64".into(),`
	`9`	`+ data_layout: "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64".into(),`
`10`	`10`	`llvm_target: "nvptx64-nvidia-cuda".into(),`
`11`	`11`	`metadata: TargetMetadata {`
`12`	`12`	`description: Some("--emit=asm generates PTX code that runs on NVIDIA GPUs".into()),`

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