Commit 7879cbb

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Rollup merge of #145078 - minxuanz:riscv-cacheline, r=samueltardieu

Fix wrong cache line size of riscv64 see https://go-review.googlesource.com/c/go/+/526659, All of riscv CPU using 64B for cache-line size.

2 parents 0c02bdc + d47b5e4 commit 7879cbbCopy full SHA for 7879cbb

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library/std/src/sync/mpmc
- utils.rs

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`‎library/std/src/sync/mpmc/utils.rs`

Lines changed: 3 additions & 5 deletions

Original file line number	Diff line number	Diff line change
`@@ -23,22 +23,20 @@ use crate::ops::{Deref, DerefMut};`
`23`	`23`	`any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "powerpc64",),`
`24`	`24`	`repr(align(128))`
`25`	`25`	`)]`
`26`		`-// arm, mips, mips64, and riscv64 have 32-byte cache line size.`
	`26`	`+// arm, mipsand mips64 have 32-byte cache line size.`
`27`	`27`	`//`
`28`	`28`	`// Sources:`
`29`	`29`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7`
`30`	`30`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7`
`31`	`31`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7`
`32`	`32`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9`
`33`		`-// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7`
`34`	`33`	`#[cfg_attr(`
`35`	`34`	`any(`
`36`	`35`	`target_arch = "arm",`
`37`	`36`	`target_arch = "mips",`
`38`	`37`	`target_arch = "mips32r6",`
`39`	`38`	`target_arch = "mips64",`
`40`	`39`	`target_arch = "mips64r6",`
`41`		`- target_arch = "riscv64",`
`42`	`40`	`),`
`43`	`41`	`repr(align(32))`
`44`	`42`	`)]`
`@@ -47,11 +45,12 @@ use crate::ops::{Deref, DerefMut};`
`47`	`45`	`// Sources:`
`48`	`46`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7`
`49`	`47`	`#[cfg_attr(target_arch = "s390x", repr(align(256)))]`
`50`		`-// x86and wasm have 64-byte cache line size.`
	`48`	`+// x86, wasm and riscv have 64-byte cache line size.`
`51`	`49`	`//`
`52`	`50`	`// Sources:`
`53`	`51`	`// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9`
`54`	`52`	`// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7`
	`53`	`+// - https://github.com/golang/go/blob/5e31f78c8a4ed1b872ddc194f0cd1ae931b37d7e/src/internal/cpu/cpu_riscv64.go#L7`
`55`	`54`	`//`
`56`	`55`	`// All others are assumed to have 64-byte cache line size.`
`57`	`56`	`#[cfg_attr(`
`@@ -64,7 +63,6 @@ use crate::ops::{Deref, DerefMut};`
`64`	`63`	`target_arch = "mips32r6",`
`65`	`64`	`target_arch = "mips64",`
`66`	`65`	`target_arch = "mips64r6",`
`67`		`- target_arch = "riscv64",`
`68`	`66`	`target_arch = "s390x",`
`69`	`67`	`)),`
`70`	`68`	`repr(align(64))`

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`‎library/std/src/sync/mpmc/utils.rs`

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