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Commit 144d6cc

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simplify things using tcx.as_lang_item

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compiler/rustc_mir_build/src
- check_tail_calls.rs

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+25

-27

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`‎compiler/rustc_mir_build/src/check_tail_calls.rs`

Lines changed: 25 additions & 27 deletions

Original file line number	Diff line number	Diff line change
`@@ -354,33 +354,31 @@ impl<'a, 'tcx> Visitor<'a, 'tcx> for TailCallCkVisitor<'a, 'tcx> {`
`354`	`354`	`}`
`355`	`355`
`356`	`356`	`fn op_trait_as_method_name(tcx: TyCtxt<'_>, trait_did: DefId) -> Option<&'static str> {`
`357`		`- let trait_did = Some(trait_did);`
`358`		`- let items = tcx.lang_items();`
`359`		`- let m = match () {`
`360`		`- _ if trait_did == items.get(LangItem::Add) => "add",`
`361`		`- _ if trait_did == items.get(LangItem::Sub) => "sub",`
`362`		`- _ if trait_did == items.get(LangItem::Mul) => "mul",`
`363`		`- _ if trait_did == items.get(LangItem::Div) => "div",`
`364`		`- _ if trait_did == items.get(LangItem::Rem) => "rem",`
`365`		`- _ if trait_did == items.get(LangItem::Neg) => "neg",`
`366`		`- _ if trait_did == items.get(LangItem::Not) => "not",`
`367`		`- _ if trait_did == items.get(LangItem::BitXor) => "bitxor",`
`368`		`- _ if trait_did == items.get(LangItem::BitAnd) => "bitand",`
`369`		`- _ if trait_did == items.get(LangItem::BitOr) => "bitor",`
`370`		`- _ if trait_did == items.get(LangItem::Shl) => "shl",`
`371`		`- _ if trait_did == items.get(LangItem::Shr) => "shr",`
`372`		`- _ if trait_did == items.get(LangItem::AddAssign) => "add_assign",`
`373`		`- _ if trait_did == items.get(LangItem::SubAssign) => "sub_assign",`
`374`		`- _ if trait_did == items.get(LangItem::MulAssign) => "mul_assign",`
`375`		`- _ if trait_did == items.get(LangItem::DivAssign) => "div_assign",`
`376`		`- _ if trait_did == items.get(LangItem::RemAssign) => "rem_assign",`
`377`		`- _ if trait_did == items.get(LangItem::BitXorAssign) => "bitxor_assign",`
`378`		`- _ if trait_did == items.get(LangItem::BitAndAssign) => "bitand_assign",`
`379`		`- _ if trait_did == items.get(LangItem::BitOrAssign) => "bitor_assign",`
`380`		`- _ if trait_did == items.get(LangItem::ShlAssign) => "shl_assign",`
`381`		`- _ if trait_did == items.get(LangItem::ShrAssign) => "shr_assign",`
`382`		`- _ if trait_did == items.get(LangItem::Index) => "index",`
`383`		`- _ if trait_did == items.get(LangItem::IndexMut) => "index_mut",`
	`357`	`+ let m = match tcx.as_lang_item(trait_did)? {`
	`358`	`+ LangItem::Add => "add",`
	`359`	`+ LangItem::Sub => "sub",`
	`360`	`+ LangItem::Mul => "mul",`
	`361`	`+ LangItem::Div => "div",`
	`362`	`+ LangItem::Rem => "rem",`
	`363`	`+ LangItem::Neg => "neg",`
	`364`	`+ LangItem::Not => "not",`
	`365`	`+ LangItem::BitXor => "bitxor",`
	`366`	`+ LangItem::BitAnd => "bitand",`
	`367`	`+ LangItem::BitOr => "bitor",`
	`368`	`+ LangItem::Shl => "shl",`
	`369`	`+ LangItem::Shr => "shr",`
	`370`	`+ LangItem::AddAssign => "add_assign",`
	`371`	`+ LangItem::SubAssign => "sub_assign",`
	`372`	`+ LangItem::MulAssign => "mul_assign",`
	`373`	`+ LangItem::DivAssign => "div_assign",`
	`374`	`+ LangItem::RemAssign => "rem_assign",`
	`375`	`+ LangItem::BitXorAssign => "bitxor_assign",`
	`376`	`+ LangItem::BitAndAssign => "bitand_assign",`
	`377`	`+ LangItem::BitOrAssign => "bitor_assign",`
	`378`	`+ LangItem::ShlAssign => "shl_assign",`
	`379`	`+ LangItem::ShrAssign => "shr_assign",`
	`380`	`+ LangItem::Index => "index",`
	`381`	`+ LangItem::IndexMut => "index_mut",`
`384`	`382`	`_ => return None,`
`385`	`383`	`};`
`386`	`384`

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Commit 144d6cc

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`‎compiler/rustc_mir_build/src/check_tail_calls.rs`

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