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Commit cdaa69e

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committed
Merge branch 'PHP-8.4'
* PHP-8.4: IR Update
2 parents 65a20d5 + c730175 commit cdaa69e

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5 files changed

+1163
-1012
lines changed

5 files changed

+1163
-1012
lines changed

‎ext/opcache/jit/ir/ir_aarch64.dasc‎

Lines changed: 17 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1383,9 +1383,16 @@ static void ir_load_local_addr(ir_ctx *ctx, ir_reg reg, ir_ref src)
13831383
ir_backend_data *data = ctx->data;
13841384
dasm_State **Dst = &data->dasm_state;
13851385
ir_reg base = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1386-
int32_t offset = IR_SPILL_POS_TO_OFFSET(ctx->ir_base[src].op3);
1386+
ir_insn *var_insn;
1387+
int32_t offset;
13871388

13881389
IR_ASSERT(ir_rule(ctx, src) == IR_STATIC_ALLOCA);
1390+
var_insn = &ctx->ir_base[src];
1391+
if (var_insn->op == IR_VADDR) {
1392+
var_insn = &ctx->ir_base[var_insn->op1];
1393+
}
1394+
IR_ASSERT(var_insn->op == IR_VAR || var_insn->op == IR_ALLOCA);
1395+
offset = IR_SPILL_POS_TO_OFFSET(var_insn->op3);
13891396
if (aarch64_may_encode_imm12(offset)) {
13901397
| add Rx(reg), Rx(base), #offset
13911398
} else {
@@ -5680,10 +5687,15 @@ static void ir_allocate_unique_spill_slots(ir_ctx *ctx)
56805687
ir_reg reg = ir_get_free_reg(constraints.tmp_regs[n].type, available);
56815688
ir_ref *ops = insn->ops;
56825689
IR_REGSET_EXCL(available, reg);
5683-
if (constraints.tmp_regs[n].num > 0
5684-
&& IR_IS_CONST_REF(ops[constraints.tmp_regs[n].num])) {
5685-
/* rematerialization */
5686-
reg |= IR_REG_SPILL_LOAD;
5690+
if (constraints.tmp_regs[n].num > 0) {
5691+
if (IR_IS_CONST_REF(ops[constraints.tmp_regs[n].num])) {
5692+
/* rematerialization */
5693+
reg |= IR_REG_SPILL_LOAD;
5694+
} else if (ctx->ir_base[ops[constraints.tmp_regs[n].num]].op == IR_ALLOCA ||
5695+
ctx->ir_base[ops[constraints.tmp_regs[n].num]].op == IR_VADDR) {
5696+
/* local address rematerialization */
5697+
reg |= IR_REG_SPILL_LOAD;
5698+
}
56875699
}
56885700
ctx->regs[i][constraints.tmp_regs[n].num] = reg;
56895701
} else if (constraints.tmp_regs[n].reg == IR_REG_SCRATCH) {

‎ext/opcache/jit/ir/ir_gcm.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1059,7 +1059,7 @@ int ir_schedule(ir_ctx *ctx)
10591059
if (ctx->flags & IR_DEBUG_SCHEDULE) {
10601060
fprintf(stderr, "After Schedule\n");
10611061
for (i = 1; i != 0; i = _next[i]) {
1062-
fprintf(stderr, "%d -> %d\n", i, _blocks[i]);
1062+
fprintf(stderr, "%d -> %d (%d)\n", i, _blocks[i], _xlat[i]);
10631063
}
10641064
}
10651065
#endif
@@ -1328,11 +1328,13 @@ int ir_schedule(ir_ctx *ctx)
13281328
new_ctx.cfg_edges = ctx->cfg_edges;
13291329
ctx->cfg_blocks = NULL;
13301330
ctx->cfg_edges = NULL;
1331+
ir_code_buffer *saved_code_buffer = ctx->code_buffer;
13311332

13321333
ir_free(ctx);
13331334
IR_ASSERT(new_ctx.consts_count == new_ctx.consts_limit);
13341335
IR_ASSERT(new_ctx.insns_count == new_ctx.insns_limit);
13351336
memcpy(ctx, &new_ctx, sizeof(ir_ctx));
1337+
ctx->code_buffer = saved_code_buffer;
13361338
ctx->flags2 |= IR_LINEAR;
13371339

13381340
ir_mem_free(_next);

‎ext/opcache/jit/ir/ir_private.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1013,8 +1013,10 @@ IR_ALWAYS_INLINE uint32_t ir_insn_len(const ir_insn *insn)
10131013
#define IR_HAS_FP_RET_SLOT (1<<10)
10141014
#define IR_16B_FRAME_ALIGNMENT (1<<11)
10151015

1016+
/* Temporary: MEM2SSA -> SCCP */
1017+
#define IR_MEM2SSA_VARS (1<<25)
1018+
10161019
/* Temporary: SCCP -> CFG */
1017-
#define IR_SCCP_DONE (1<<25)
10181020
#define IR_CFG_REACHABLE (1<<26)
10191021

10201022
/* Temporary: Dominators -> Loops */

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