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fuzzer generate non-combinational code w/ --generator=combinational options #4361

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bugSomething isn't working or is incorrect codegenRelated to emitting (System)Verilog. fuzz

Description

XLS fuzzer crasher: codegen_main UNIMPLEMENTED error.

Error Message

Error: UNIMPLEMENTED: Proc combinational generator only supports streaming output channels which can be determined to be mutually exclusive, got 2 output channels which were not proven to be mutually exclusive; Running pass #6: Channel I/O to port lowering pass [short: channel_to_port_io_lowering]; Failed as part of compound pass block_conversion #0; Running pass #0: Top level codegen v1.5 block conversion pipeline [short: block_conversion]

Minimized DSLX

proc main {
 x6: chan<bool> out;
 x18: chan<u5> out;
 config(x6: chan<bool> out, x18: chan<u5> out) {
 (x6, x18)
 }
 init {
 ()
 }
 next(x0: ()) {
 let tok: token = join();
 let x7: token = send_if(tok, x6, true, true);
 let x19: token = send_if(tok, x18, true, u5:1);
 x0
 }
}

Reproduction Steps

Run run_crasher with the minimized DSLX and the following options (which match the crasher config):
--generator=combinational

Root Cause Analysis

The failure occurs in xls/codegen_v_1_5/channel_to_port_io_lowering_pass.cc at line 1668.

 if (needs_one_shot_logic) {
 if (options.codegen_options.generate_combinational()) {
 return absl::UnimplementedError(absl::StrFormat(
 "Proc combinational generator only supports streaming output "
 "channels which can be determined to be mutually exclusive, got %d "
 "output channels which were not proven to be mutually exclusive",
 outgoing_channel_count));
 }

If a proc has multiple streaming output channels (outgoing_channel_count > 1) and they cannot be proven to be mutually exclusive (AreStreamingOutputsMutuallyExclusive returns false), the compiler needs to insert "one-shot logic" to ensure each output is sent at most once.

However, one-shot logic requires state (registers) to track which sends have completed.
In combinational mode (options.codegen_options.generate_combinational() is true), we cannot insert registers.
Therefore, the combinational generator cannot support this case and returns UnimplementedError.

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    bugSomething isn't working or is incorrect codegenRelated to emitting (System)Verilog. fuzz

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