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pci: document potential contention on PCI bus lock

We have a single lock for all devices on the PCI bus that serializes reads and writes on the devices' PCI configuration space and BARs. This should not be a problem at the moment. It should be out of any hot path and only up until we are setting up devices. However, add a comment that mentions the existence of the contention so that we keep it in mind for the futuer (and maybe perform some profiling). Signed-off-by: Babis Chalios <bchalios@amazon.es>

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src/pci/src
- bus.rs

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`‎src/pci/src/bus.rs`

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Original file line number	Diff line number	Diff line change
`@@ -161,6 +161,9 @@ impl PciConfigIo {`
`161`	`161`	`return 0xffff_ffff;`
`162`	`162`	`}`
`163`	`163`
	`164`	`+ // NOTE: Potential contention among vCPU threads on this lock. This should not`
	`165`	`+ // be a problem currently, since we mainly access this when we are setting up devices.`
	`166`	`+ // We might want to do some profiling to ensure this does not become a bottleneck.`
`164`	`167`	`self.pci_bus`
`165`	`168`	`.as_ref()`
`166`	`169`	`.lock()`
`@@ -195,6 +198,9 @@ impl PciConfigIo {`
`195`	`198`	`return None;`
`196`	`199`	`}`
`197`	`200`
	`201`	`+ // NOTE: Potential contention among vCPU threads on this lock. This should not`
	`202`	`+ // be a problem currently, since we mainly access this when we are setting up devices.`
	`203`	`+ // We might want to do some profiling to ensure this does not become a bottleneck.`
`198`	`204`	`let pci_bus = self.pci_bus.as_ref().lock().unwrap();`
`199`	`205`	`if let Some(d) = pci_bus.devices.get(&(device as u32)) {`
`200`	`206`	`let mut device = d.lock().unwrap();`

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Commit b052ae4

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`‎src/pci/src/bus.rs`

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