Hey everyone,
I'm always frustrated when dealing with verilog netlists, that have buses as inputs. HAL does not allow me to write a verilog netlist, that has module inputs or outputs with a certain bus width.

At the moment, a netlist with:
input [1:0] a;
is written as:
input a(0);
input a(1);

This limits interoperability with commercial tools that require the first notation to denote buses.
It would be great to have some notion to detect buses, such as grouped input pins.
In the following netlist I would expect the groupings:
a, b, y

input_grouping_example.txt