Hints: Add VHDL/Verilog/SystemVerilog syntax #161

$ loc 
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 Language Files Lines Blank Comment Code
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 Plain Text 3 9000 0 0 9000
 TeX 1 1354 299 9 1046
 Coq 2 278 42 0 236
 Makefile 1 156 31 0 125
 C 1 132 24 0 108
 Markdown 1 11 3 0 8
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 Total 9 10931 399 9 10523
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Note

I see other problem with the Verilog language. The loc tool detects the Coq language because both have the same extension: .v.