Commit f77cd4d

author

Sandy

authored

Merge pull request #209 from openset/develop

Update: Reverse String

2 parents 9157e66 + f9e02de commit f77cd4dCopy full SHA for f77cd4d

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+27

-15

lines changed

+27

-15

lines changed

Lines changed: 3 additions & 5 deletions

Original file line number	Diff line number	Diff line change
`@@ -1,9 +1,7 @@`
`1`	`1`	`package reverse_string`
`2`	`2`
`3`		`-func reverseString(s string) string {`
`4`		`- runes := []rune(s)`
`5`		`- for i, j := 0, len(runes)-1; i < j; i, j = i+1, j-1 {`
`6`		`- runes[i], runes[j] = runes[j], runes[i]`
	`3`	`+func reverseString(s []byte) {`
	`4`	`+ for i, j := 0, len(s)-1; i < j; i, j = i+1, j-1 {`
	`5`	`+ s[i], s[j] = s[j], s[i]`
`7`	`6`	`}`
`8`		`- return string(runes)`
`9`	`7`	`}`

Lines changed: 24 additions & 10 deletions

Original file line number	Diff line number	Diff line change
`@@ -1,18 +1,32 @@`
`1`	`1`	`package reverse_string`
`2`	`2`
`3`		`-import "testing"`
	`3`	`+import (`
	`4`	`+ "reflect"`
	`5`	`+ "testing"`
	`6`	`+)`
	`7`	`+`
	`8`	`+type caseType struct {`
	`9`	`+ input []byte`
	`10`	`+ expected []byte`
	`11`	`+}`
`4`	`12`
`5`	`13`	`func TestReverseString(t *testing.T) {`
`6`		`- tests := map[string]string{`
`7`		`- "hello, world": "dlrow ,olleh",`
`8`		`- "你好,世界": "界世,好你",`
`9`		`- "A man, a plan, a canal: Panama": "amanaP :lanac a ,nalp a ,nam A",`
	`14`	`+ tests := [...]caseType{`
	`15`	`+ {`
	`16`	`+ input: []byte{'h', 'e', 'l', 'l', 'o'},`
	`17`	`+ expected: []byte{'o', 'l', 'l', 'e', 'h'},`
	`18`	`+ },`
	`19`	`+ {`
	`20`	`+ input: []byte{'H', 'a', 'n', 'n', 'a', 'h'},`
	`21`	`+ expected: []byte{'h', 'a', 'n', 'n', 'a', 'H'},`
	`22`	`+ },`
`10`	`23`	`}`
`11`		`-`
`12`		`- for input, expected := range tests {`
`13`		`- output := reverseString(input)`
`14`		`- if output != expected {`
`15`		`- t.Fatalf("input: %v, output: %v, expected: %v", input, output, expected)`
	`24`	`+ for _, tc := range tests {`
	`25`	`+ output := make([]byte, len(tc.input))`
	`26`	`+ copy(output, tc.input)`
	`27`	`+ reverseString(output)`
	`28`	`+ if !reflect.DeepEqual(output, tc.expected) {`
	`29`	`+ t.Fatalf("input: %v, output: %v, expected: %v", tc.input, output, tc.expected)`
`16`	`30`	`}`
`17`	`31`	`}`
`18`	`32`	`}`

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