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Commit 96ccceb

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RPC: Configure M4 memory as strongly ordered if booting from SDRAM.
If the Cortex-M4 core is booting from SDRAM, the memory region must be configured as Strongly Ordered. Note that the Cortex-M4 core does not seem to implement speculative prefetching, so there is no need to protect the whole region from speculative prefetching with a second MPU region. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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‎libraries/RPC/src/RPC.cpp‎

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@@ -163,6 +163,35 @@ int RPCClass::begin() {
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#endif
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#ifdef CORE_CM4
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#if (CM4_BINARY_START >= 0x60000000) && (CM4_BINARY_START < 0xe0000000)
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class M4Init {
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public:
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M4Init() {
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// If the Cortex-M4 core is booting from SDRAM, the memory region must be
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// configured as Strongly Ordered. Note that the Cortex-M4 core does not
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// seem to implement speculative prefetching, so there is no need to protect
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// the whole region from speculative prefetching with a second MPU region.
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HAL_MPU_Disable();
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MPU_Region_InitTypeDef MPU_InitStruct;
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MPU_InitStruct.Number = MPU_REGION_NUMBER1;
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = CM4_BINARY_START;
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MPU_InitStruct.Size = MPU_REGION_SIZE_1MB;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.SubRegionDisable = 0x00;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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}
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};
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M4Init __m4init __attribute__ ((init_priority (101)));
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#endif
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int RPCClass::begin() {
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eventThread = new rtos::Thread(osPriorityHigh, 16*1024, nullptr, "rpc_evt");
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eventThread->start(&eventHandler);

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