Commit 907d68c

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libraries/Arduino_H7_Video: Fix the DSI PLL configuration.

With the current configuration (NDIV=125, PLLIDF=3, PLLODF=1) the DSI PLL outputs an out of spec 83MHz clock. This fix sets the output clock to the max supported clock of 62.5MHz, according to the datasheet. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>

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libraries/Arduino_H7_Video/src
- dsi.cpp

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`‎libraries/Arduino_H7_Video/src/dsi.cpp‎`

Lines changed: 2 additions & 2 deletions

Original file line number	Diff line number	Diff line change
`@@ -48,7 +48,7 @@ static void dsi_layerInit(uint16_t LayerIndex, uint32_t FB_Address);`
`48`	`48`	`int dsi_init(uint8_t bus, struct edid edid, struct display_timing dt) {`
`49`	`49`	`#ifdef ARDUINO_GIGA`
`50`	`50`	`static const uint32_t DSI_PLLNDIV = 125;`
`51`		`- static const uint32_t DSI_PLLIDF = DSI_PLL_IN_DIV3;`
	`51`	`+ static const uint32_t DSI_PLLIDF = DSI_PLL_IN_DIV4;`
`52`	`52`	`static const uint32_t DSI_PLLODF = DSI_PLL_OUT_DIV1;`
`53`	`53`	`static const uint32_t DSI_TXEXCAPECLOCKDIV = 4;`
`54`	`54`	`#undef HSE_VALUE`
`@@ -412,4 +412,4 @@ extern "C" void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) {`
`412`	`412`	`reloadLTDC_status = 1;`
`413`	`413`	`}`
`414`	`414`
`415`		`-/** END OF FILE **/`
	`415`	`+/** END OF FILE **/`

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Commit 907d68c

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`‎libraries/Arduino_H7_Video/src/dsi.cpp‎`

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