According to the TI description of I2C protocol (http://www.ti.com/lit/an/slva704/slva704.pdf page 5, sect 2.3, bullet 4) the receiver controls ACK/NACK, not the transmitter.

The fall-through case TW_ST_DATA_ACK in twi.c in the ISR is setting ACK/NACK based on the state of the 32-byte buffer (have all bytes been written). I believe this is backwards based on the spec, the ST code should continue sending bytes from the buffer until the master-receiver asserts NACK followed by STOP (page 6, figure 7 of the same doc).

I encountered this issue trying to interface with a master platform that is using a DMA engine to read a variable number of bytes from the I2C slave (16 to 1024). Unless the slave knows exactly how many bytes to send, the master has to wake up and generate another interrupt.