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Commit a35f1c8

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RISC-V: Add 27 extensions to be stabilized
Because unstable "B" (incorrectly named as `zb`) was there, this commit adds 28 minus one ("B") new extensions to be stabilized. This commit directly corresponds to rust-lang/rust#145948. References: 1. RISC-V Instruction Set Manual (version 20250508): <https://github.com/riscv/riscv-isa-manual/tree/20250508> 2. RISC-V Profiles (version 1.0 - RVA23 is not stabilized at the time): <https://github.com/riscv/riscv-profiles/tree/v1.0> 3. RISC-V Profiles (RVA23/RVB23-ratified version): <https://github.com/riscv/riscv-profiles/tree/rva23-rvb23-ratified>
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‎src/attributes/codegen.md

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@@ -427,17 +427,43 @@ in another manual hosted on the [RISC-V GitHub Account].
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Feature | Implicitly Enables | Description
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------------|---------------------|-------------------
430-
`a` | | [A][rv-a] --- Atomic instructions
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`a` | `zaamo`, `zalrsc` | [A][rv-a] --- Atomic instructions
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`b` | `zba`, `zbc`, `zbs` | [B][rv-b] --- Bit Manipulation instructions
432-
`c` | | [C][rv-c] --- Compressed instructions
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`c` | `zca` | [C][rv-c] --- Compressed instructions
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`m` | | [M][rv-m] --- Integer Multiplication and Division instructions
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`za64rs` | `za128rs` | [Za64rs][rv-za64rs] --- Platform Behavior: Naturally aligned Reservation sets with ≦ 64 Bytes
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`za128rs` | | [Za128rs][rv-za128rs] --- Platform Behavior: Naturally aligned Reservation sets with ≦ 128 Bytes
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`zaamo` | | [Zaamo][rv-zaamo] --- Atomic Memory Operation instructions
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`zabha` | `zaamo` | [Zabha][rv-zabha] --- Byte and Halfword Atomic Memory Operation instructions
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`zalrsc` | | [Zalrsc][rv-zalrsc] --- Load-Reserved/Store-Conditional instructions
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`zama16b` | | [Zama16b][rv-zama16b] --- Platform Behavior: Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic
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`zawrs` | | [Zawrs][rv-zawrs] --- Wait-on-Reservation-Set instructions
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`zba` | | [Zba][rv-zba] --- Address Generation instructions
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`zbb` | | [Zbb][rv-zbb] --- Basic bit-manipulation
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`zbc` | `zbkc` | [Zbc][rv-zbc] --- Carry-less multiplication
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`zbkb` | | [Zbkb][rv-zbkb] --- Bit Manipulation Instructions for Cryptography
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`zbkc` | | [Zbkc][rv-zbkc] --- Carry-less multiplication for Cryptography
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`zbkx` | | [Zbkx][rv-zbkx] --- Crossbar permutations
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`zbs` | | [Zbs][rv-zbs] --- Single-bit instructions
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`zca` | | [Zca][rv-zca] --- Compressed instructions: integer part subset
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`zcb` | `zca` | [Zcb][rv-zcb] --- Simple Code-size Saving Compressed instructions
450+
`zcmop` | `zca` | [Zcmop][rv-zcmop] --- Compressed May-Be-Operations
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`zic64b` | | [Zic64b][rv-zic64b] --- Platform Behavior: Naturally aligned 64 byte Cache blocks
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`zicbom` | | [Zicbom][rv-zicbom] --- Cache-Block Management instructions
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`zicbop` | | [Zicbop][rv-zicbop] --- Cache-Block Prefetch Hint instructions
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`zicboz` | | [Zicboz][rv-zicboz] --- Cache-Block Zero instruction
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`ziccamoa` | | [Ziccamoa][rv-ziccamoa] --- Platform Behavior: Cacheable and Coherent Main memory supports all basic atomic operations
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`ziccif` | | [Ziccif][rv-ziccif] --- Platform Behavior: Cacheable and Coherent Main memory supports instruction fetch and fetches of naturally aligned power-of-2 sizes up to `min(ILEN,XLEN)` are atomic
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`zicclsm` | | [Zicclsm][rv-zicclsm] --- Platform Behavior: Cacheable and Coherent Main memory supports misaligned load/store accesses
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`ziccrse` | | [Ziccrse][rv-ziccrse] --- Platform Behavior: Cacheable and Coherent Main memory guarantees eventual success on LR/SC sequences
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`zicntr` | `zicsr` | [Zicntr][rv-zicntr] --- Base Counters and Timers
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`zicond` | | [Zicond][rv-zicond] --- Integer Conditional Operation instructions
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`zicsr` | | [Zicsr][rv-zicsr] --- Control and Status Register (CSR) instructions
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`zifencei` | | [Zifencei][rv-zifencei] --- Instruction-Fetch Fence instruction
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`zihintntl` | | [Zihintntl][rv-zihintntl] --- Non-Temporal Locality Hint instructions
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`zihintpause` | | [Zihintpause][rv-zihintpause] --- Pause Hint instruction
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`zihpm` | `zicsr` | [Zihpm][rv-zihpm] --- Hardware Performance Counters
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`zimop` | | [Zimop][rv-zimop] --- May-Be-Operations
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`zk` | `zkn`, `zkr`, `zks`, `zkt`, `zbkb`, `zbkc`, `zkbx` | [Zk][rv-zk] --- Scalar Cryptography
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`zkn` | `zknd`, `zkne`, `zknh`, `zbkb`, `zbkc`, `zkbx` | [Zkn][rv-zkn] --- NIST Algorithm suite extension
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`zknd` | | [Zknd][rv-zknd] --- NIST Suite: AES Decryption
@@ -448,20 +474,47 @@ Feature | Implicitly Enables | Description
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`zksed` | | [Zksed][rv-zksed] --- ShangMi Suite: SM4 Block Cipher Instructions
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`zksh` | | [Zksh][rv-zksh] --- ShangMi Suite: SM3 Hash Function Instructions
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`zkt` | | [Zkt][rv-zkt] --- Data Independent Execution Latency Subset
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`ztso` | | [Ztso][rv-ztso] --- Total Store Ordering
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<!-- Keep links near each table to make it easier to move and update. -->
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[rv-a]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc
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[rv-b]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-c]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/c-st-ext.adoc
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[rv-m]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/m-st-ext.adoc
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[rv-za64rs]: https://github.com/riscv/riscv-profiles/blob/rva23-rvb23-ratified/src/rva23-profile.adoc
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[rv-za128rs]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
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[rv-zaamo]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc
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[rv-zabha]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zabha.adoc
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[rv-zalrsc]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/a-st-ext.adoc
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[rv-zama16b]: https://github.com/riscv/riscv-profiles/blob/rva23-rvb23-ratified/src/rva23-profile.adoc
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[rv-zawrs]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zawrs.adoc
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[rv-zba]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbb]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbc]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbkb]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbkc]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbkx]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zbs]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/b-st-ext.adoc
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[rv-zca]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zc.adoc
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[rv-zcb]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zc.adoc
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[rv-zcmop]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zimop.adoc
502+
[rv-zic64b]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
503+
[rv-zicbom]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/cmo.adoc
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[rv-zicbop]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/cmo.adoc
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[rv-zicboz]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/cmo.adoc
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[rv-ziccamoa]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
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[rv-ziccif]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
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[rv-zicclsm]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
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[rv-ziccrse]: https://github.com/riscv/riscv-profiles/blob/v1.0/profiles.adoc
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[rv-zicntr]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/counters.adoc
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[rv-zicond]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zicond.adoc
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[rv-zicsr]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zicsr.adoc
513+
[rv-zifencei]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zifencei.adoc
514+
[rv-zihintntl]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zihintntl.adoc
515+
[rv-zihintpause]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zihintpause.adoc
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[rv-zihpm]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/counters.adoc
517+
[rv-zimop]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/zimop.adoc
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[rv-zk]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
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[rv-zkn]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
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[rv-zkne]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
@@ -472,6 +525,7 @@ Feature | Implicitly Enables | Description
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[rv-zksed]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
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[rv-zksh]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
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[rv-zkt]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/scalar-crypto.adoc
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[rv-ztso]: https://github.com/riscv/riscv-isa-manual/blob/20250508/src/ztso-st-ext.adoc
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r[attributes.codegen.target_feature.wasm]
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#### `wasm32` or `wasm64`

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