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Commit 93a118c

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Fix Wire.setClock() causing assert (espressif#8777)
* Fix Wire.setClock() causing assert When Wire.setClock() is called after Wire.begin() an assert is triggered due to changes in clock calculations * Fix typo
1 parent 7438c6e commit 93a118c

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+18
-11
lines changed

1 file changed

+18
-11
lines changed

‎cores/esp32/esp32-hal-i2c.c‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,13 @@
3030
#include "driver/i2c.h"
3131
#include "esp32-hal-periman.h"
3232

33+
#if SOC_I2C_SUPPORT_APB || SOC_I2C_SUPPORT_XTAL
34+
#include "esp_private/esp_clk.h"
35+
#endif
36+
#if SOC_I2C_SUPPORT_RTC
37+
#include "clk_ctrl_os.h"
38+
#endif
39+
3340
typedef volatile struct {
3441
bool initialized;
3542
uint32_t frequency;
@@ -303,11 +310,6 @@ esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency){
303310
} else if(frequency > 1000000UL){
304311
frequency = 1000000UL;
305312
}
306-
// Freq limitation when using different clock sources
307-
#define I2C_CLK_LIMIT_REF_TICK (1 * 1000 * 1000 / 20) /*!< Limited by REF_TICK, no more than REF_TICK/20*/
308-
#define I2C_CLK_LIMIT_APB (80 * 1000 * 1000 / 20) /*!< Limited by APB, no more than APB/20*/
309-
#define I2C_CLK_LIMIT_RTC (20 * 1000 * 1000 / 20) /*!< Limited by RTC, no more than RTC/20*/
310-
#define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /*!< Limited by RTC, no more than XTAL/20*/
311313

312314
typedef struct {
313315
soc_module_clk_t clk; /*!< I2C source clock */
@@ -332,22 +334,22 @@ esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency){
332334
} i2c_sclk_t;
333335

334336
// i2c clock characteristic, The order is the same as i2c_sclk_t.
335-
statici2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = {
337+
i2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = {
336338
{0, 0},
337339
#if SOC_I2C_SUPPORT_APB
338-
{SOC_MOD_CLK_APB, I2C_CLK_LIMIT_APB}, /*!< I2C APB clock characteristic*/
340+
{SOC_MOD_CLK_APB, esp_clk_apb_freq()}, /*!< I2C APB clock characteristic*/
339341
#endif
340342
#if SOC_I2C_SUPPORT_XTAL
341-
{SOC_MOD_CLK_XTAL, I2C_CLK_LIMIT_XTAL}, /*!< I2C XTAL characteristic*/
343+
{SOC_MOD_CLK_XTAL, esp_clk_xtal_freq()}, /*!< I2C XTAL characteristic*/
342344
#endif
343345
#if SOC_I2C_SUPPORT_RTC
344-
{SOC_MOD_CLK_RC_FAST, I2C_CLK_LIMIT_RTC}, /*!< I2C 20M RTC characteristic*/
346+
{SOC_MOD_CLK_RC_FAST, periph_rtc_dig_clk8m_get_freq()}, /*!< I2C 20M RTC characteristic*/
345347
#endif
346348
#if SOC_I2C_SUPPORT_REF_TICK
347-
{SOC_MOD_CLK_REF_TICK, I2C_CLK_LIMIT_REF_TICK},/*!< I2C REF_TICK characteristic*/
349+
{SOC_MOD_CLK_REF_TICK, REF_CLK_FREQ},/*!< I2C REF_TICK characteristic*/
348350
#endif
349351
};
350-
352+
351353
i2c_sclk_t src_clk = I2C_SCLK_DEFAULT;
352354
ret = ESP_OK;
353355
for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) {
@@ -367,6 +369,11 @@ esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency){
367369
} else {
368370
i2c_hal_context_t hal;
369371
hal.dev = I2C_LL_GET_HW(i2c_num);
372+
#if SOC_I2C_SUPPORT_RTC
373+
if(src_clk == I2C_SCLK_RTC){
374+
periph_rtc_dig_clk8m_enable();
375+
}
376+
#endif
370377
i2c_hal_set_bus_timing(&(hal), frequency, i2c_clk_alloc[src_clk].clk, i2c_clk_alloc[src_clk].clk_freq);
371378
bus[i2c_num].frequency = frequency;
372379
//Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2

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