Hi Obijuan,

first: compliments for your Tutorial. Best Tutorial on Verilog with very nice examples.

I have a question on T27-Memoria ROM generica.
In genrom.v you use posedge clk to read ROM
In genromleds.v you use negedge clk to advance addr.

Why do you mix posedge and negedge clk in one project.
In T22-Reglas de diseno sincrono you say, that it is not a good Idea to use both edgelevel detection.

Is it wrong to use only posedge on genrom.v and genromleds.v?

Greetings
Micha