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Commit d68687c

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borsMuscraft
authored andcommitted
Auto merge of rust-lang#146879 - Zalathar:rollup-vm97j8b, r=Zalathar
Rollup of 9 pull requests Successful merges: - rust-lang#145411 (regression test for Cow<[u8]> layout) - rust-lang#146397 (std_detect on Darwin AArch64: update features) - rust-lang#146791 (emit attribute for readonly non-pure inline assembly) - rust-lang#146831 (Support ctr and lr as clobber-only registers in PowerPC inline assembly) - rust-lang#146838 (Introduce "wrapper" helpers to rustdoc) - rust-lang#146845 (Add self-profile events for target-machine creation) - rust-lang#146846 (btree InternalNode::new safety comments) - rust-lang#146858 (Make mips64el-unknown-linux-muslabi64 link dynamically) - rust-lang#146878 (assert_unsafe_precondition: fix some incorrect check_language_ub) r? `@ghost` `@rustbot` modify labels: rollup
2 parents 9574db9 + dd61830 commit d68687c

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30 files changed

+948
-462
lines changed

30 files changed

+948
-462
lines changed

‎compiler/rustc_codegen_gcc/src/asm.rs‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -698,8 +698,12 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
698698
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
699699
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
700700
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => "v",
701-
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
702-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
701+
InlineAsmRegClass::PowerPC(
702+
PowerPCInlineAsmRegClass::cr
703+
| PowerPCInlineAsmRegClass::ctr
704+
| PowerPCInlineAsmRegClass::lr
705+
| PowerPCInlineAsmRegClass::xer,
706+
) => {
703707
unreachable!("clobber-only")
704708
}
705709
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -777,8 +781,12 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
777781
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
778782
cx.type_vector(cx.type_i32(), 4)
779783
}
780-
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
781-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
784+
InlineAsmRegClass::PowerPC(
785+
PowerPCInlineAsmRegClass::cr
786+
| PowerPCInlineAsmRegClass::ctr
787+
| PowerPCInlineAsmRegClass::lr
788+
| PowerPCInlineAsmRegClass::xer,
789+
) => {
782790
unreachable!("clobber-only")
783791
}
784792
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),

‎compiler/rustc_codegen_llvm/src/asm.rs‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -340,8 +340,8 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
340340
attrs.push(llvm::AttributeKind::WillReturn.create_attr(self.cx.llcx));
341341
} else if options.contains(InlineAsmOptions::NOMEM) {
342342
attrs.push(llvm::MemoryEffects::InaccessibleMemOnly.create_attr(self.cx.llcx));
343-
} else {
344-
// LLVM doesn't have an attribute to represent ReadOnly + SideEffect
343+
} else if options.contains(InlineAsmOptions::READONLY){
344+
attrs.push(llvm::MemoryEffects::ReadOnlyNotPure.create_attr(self.cx.llcx));
345345
}
346346
attributes::apply_to_callsite(result, llvm::AttributePlace::Function, &{ attrs });
347347

@@ -662,7 +662,12 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
662662
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
663663
PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
664664
PowerPC(PowerPCInlineAsmRegClass::vreg) => "v",
665-
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
665+
PowerPC(
666+
PowerPCInlineAsmRegClass::cr
667+
| PowerPCInlineAsmRegClass::ctr
668+
| PowerPCInlineAsmRegClass::lr
669+
| PowerPCInlineAsmRegClass::xer,
670+
) => {
666671
unreachable!("clobber-only")
667672
}
668673
RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -830,7 +835,12 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
830835
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
831836
PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
832837
PowerPC(PowerPCInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i32(), 4),
833-
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
838+
PowerPC(
839+
PowerPCInlineAsmRegClass::cr
840+
| PowerPCInlineAsmRegClass::ctr
841+
| PowerPCInlineAsmRegClass::lr
842+
| PowerPCInlineAsmRegClass::xer,
843+
) => {
834844
unreachable!("clobber-only")
835845
}
836846
RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),

‎compiler/rustc_codegen_llvm/src/back/write.rs‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,9 @@ pub(crate) fn target_machine_factory(
204204
optlvl: config::OptLevel,
205205
target_features: &[String],
206206
) -> TargetMachineFactoryFn<LlvmCodegenBackend> {
207+
// Self-profile timer for creating a _factory_.
208+
let _prof_timer = sess.prof.generic_activity("target_machine_factory");
209+
207210
let reloc_model = to_llvm_relocation_model(sess.relocation_model());
208211

209212
let (opt_level, _) = to_llvm_opt_settings(optlvl);
@@ -259,6 +262,9 @@ pub(crate) fn target_machine_factory(
259262
.into_string()
260263
.unwrap_or_default();
261264
let command_line_args = quote_command_line_args(&sess.expanded_args);
265+
// Self-profile counter for the number of bytes produced by command-line quoting.
266+
// Values are summed, so the summary result is cumulative across all TM factories.
267+
sess.prof.artifact_size("quoted_command_line_args", "-", command_line_args.len() as u64);
262268

263269
let debuginfo_compression = sess.opts.debuginfo_compression.to_string();
264270
match sess.opts.debuginfo_compression {
@@ -281,7 +287,11 @@ pub(crate) fn target_machine_factory(
281287

282288
let use_wasm_eh = wants_wasm_eh(sess);
283289

290+
let prof = SelfProfilerRef::clone(&sess.prof);
284291
Arc::new(move |config: TargetMachineFactoryConfig| {
292+
// Self-profile timer for invoking a factory to create a target machine.
293+
let _prof_timer = prof.generic_activity("target_machine_factory_inner");
294+
285295
let path_to_cstring_helper = |path: Option<PathBuf>| -> CString {
286296
let path = path.unwrap_or_default();
287297
let path = path_mapping

‎compiler/rustc_codegen_llvm/src/llvm/ffi.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -710,6 +710,7 @@ pub(crate) enum MemoryEffects {
710710
None,
711711
ReadOnly,
712712
InaccessibleMemOnly,
713+
ReadOnlyNotPure,
713714
}
714715

715716
/// LLVMOpcode

‎compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -553,6 +553,7 @@ enum class LLVMRustMemoryEffects {
553553
None,
554554
ReadOnly,
555555
InaccessibleMemOnly,
556+
ReadOnlyNotPure,
556557
};
557558

558559
extern "C" LLVMAttributeRef
@@ -568,6 +569,10 @@ LLVMRustCreateMemoryEffectsAttr(LLVMContextRef C,
568569
case LLVMRustMemoryEffects::InaccessibleMemOnly:
569570
return wrap(Attribute::getWithMemoryEffects(
570571
*unwrap(C), MemoryEffects::inaccessibleMemOnly()));
572+
case LLVMRustMemoryEffects::ReadOnlyNotPure:
573+
return wrap(Attribute::getWithMemoryEffects(
574+
*unwrap(C),
575+
MemoryEffects::readOnly() | MemoryEffects::inaccessibleMemOnly()));
571576
default:
572577
report_fatal_error("bad MemoryEffects.");
573578
}

‎compiler/rustc_span/src/symbol.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -794,6 +794,7 @@ symbols! {
794794
ctlz,
795795
ctlz_nonzero,
796796
ctpop,
797+
ctr,
797798
cttz,
798799
cttz_nonzero,
799800
custom_attribute,
@@ -1333,6 +1334,7 @@ symbols! {
13331334
loongarch_target_feature,
13341335
loop_break_value,
13351336
loop_match,
1337+
lr,
13361338
lt,
13371339
m68k_target_feature,
13381340
macro_at_most_once_rep,

‎compiler/rustc_target/src/asm/mod.rs‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1260,11 +1260,12 @@ impl InlineAsmClobberAbi {
12601260
v8, v9, v10, v11, v12, v13, v14,
12611261
v15, v16, v17, v18, v19,
12621262

1263-
// cr0-cr1, cr5-cr7, xer
1263+
// cr0-cr1, cr5-cr7, ctr, lr, xer
12641264
cr0, cr1,
12651265
cr5, cr6, cr7,
1266+
ctr,
1267+
lr,
12661268
xer,
1267-
// lr and ctr are reserved
12681269
}
12691270
},
12701271
InlineAsmClobberAbi::S390x => clobbered_regs! {

‎compiler/rustc_target/src/asm/powerpc.rs‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@ def_reg_class! {
1313
freg,
1414
vreg,
1515
cr,
16+
ctr,
17+
lr,
1618
xer,
1719
}
1820
}
@@ -56,7 +58,7 @@ impl PowerPCInlineAsmRegClass {
5658
altivec: VecI8(16), VecI16(8), VecI32(4), VecF32(4);
5759
vsx: F32, F64, VecI64(2), VecF64(2);
5860
},
59-
Self::cr | Self::xer => &[],
61+
Self::cr | Self::ctr | Self::lr | Self::xer => &[],
6062
}
6163
}
6264
}
@@ -195,6 +197,8 @@ def_regs! {
195197
cr5: cr = ["cr5"],
196198
cr6: cr = ["cr6"],
197199
cr7: cr = ["cr7"],
200+
ctr: ctr = ["ctr"],
201+
lr: lr = ["lr"],
198202
xer: xer = ["xer"],
199203
#error = ["r1", "1", "sp"] =>
200204
"the stack pointer cannot be used as an operand for inline asm",
@@ -206,10 +210,6 @@ def_regs! {
206210
"r30 is used internally by LLVM and cannot be used as an operand for inline asm",
207211
#error = ["r31", "31", "fp"] =>
208212
"the frame pointer cannot be used as an operand for inline asm",
209-
#error = ["lr"] =>
210-
"the link register cannot be used as an operand for inline asm",
211-
#error = ["ctr"] =>
212-
"the counter register cannot be used as an operand for inline asm",
213213
#error = ["vrsave"] =>
214214
"the vrsave register cannot be used as an operand for inline asm",
215215
}
@@ -247,6 +247,8 @@ impl PowerPCInlineAsmReg {
247247
(v24, "24"), (v25, "25"), (v26, "26"), (v27, "27"), (v28, "28"), (v29, "29"), (v30, "30"), (v31, "31");
248248
(cr, "cr");
249249
(cr0, "0"), (cr1, "1"), (cr2, "2"), (cr3, "3"), (cr4, "4"), (cr5, "5"), (cr6, "6"), (cr7, "7");
250+
(ctr, "ctr");
251+
(lr, "lr");
250252
(xer, "xer");
251253
}
252254
}

‎compiler/rustc_target/src/spec/targets/mips64el_unknown_linux_muslabi64.rs‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,6 @@ pub(crate) fn target() -> Target {
55
base.cpu = "mips64r2".into();
66
base.features = "+mips64r2,+xgot".into();
77
base.max_atomic_width = Some(64);
8-
// FIXME(compiler-team#422): musl targets should be dynamically linked by default.
9-
base.crt_static_default = true;
108
Target {
119
// LLVM doesn't recognize "muslabi64" yet.
1210
llvm_target: "mips64el-unknown-linux-musl".into(),

‎library/alloc/src/collections/btree/node.rs‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,10 +117,11 @@ impl<K, V> InternalNode<K, V> {
117117
/// initialized and valid edge. This function does not set up
118118
/// such an edge.
119119
unsafe fn new<A: Allocator + Clone>(alloc: A) -> Box<Self, A> {
120+
let mut node = Box::<Self, _>::new_uninit_in(alloc);
120121
unsafe {
121-
let mut node = Box::<Self, _>::new_uninit_in(alloc);
122-
// We only need to initialize the data; the edges are MaybeUninit.
122+
// SAFETY: argument points to the `node.data` `LeafNode`
123123
LeafNode::init(&raw mut (*node.as_mut_ptr()).data);
124+
// SAFETY: `node.data` was just initialized and `node.edges` is MaybeUninit.
124125
node.assume_init()
125126
}
126127
}

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