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Minor modernization for README.barrier.
2021年3月12日 02:24:28 +0000 (15:24 +1300)
2021年3月12日 02:36:16 +0000 (15:36 +1300)
Itanium is very uncommon and being discontinued. ARM is everywhere.
Prefer ARM as an example of an architecture with weak memory ordering.


diff --git a/src/backend/storage/lmgr/README.barrier b/src/backend/storage/lmgr/README.barrier
index 4e37a4acbe7a77c3c20977bf20fdc58f9c4b98c5..e73d6799abcaafd33024191a208d5832fc5fb07d 100644 (file)
--- a/src/backend/storage/lmgr/README.barrier
+++ b/src/backend/storage/lmgr/README.barrier
@@ -38,7 +38,7 @@ Surprisingly, however, the second backend could also end up with foo = 0
and bar = 1. The compiler might swap the order of the two stores performed
by the first backend, or the two loads performed by the second backend.
Even if it doesn't, on a machine with weak memory ordering (such as PowerPC
-or Itanium) the CPU might choose to execute either the loads or the stores
+or ARM) the CPU might choose to execute either the loads or the stores
out of order. This surprising result can lead to bugs.
A common pattern where this actually does result in a bug is when adding items
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