java aliasing rules

Sat Mar 30 13:55:00 GMT 2002

On Sat, Mar 30, 2002 at 09:35:54AM -0500, Jeff Sturm wrote:
> Wouldn't accessing r9 immediately after the load cause a pipeline stall?

Yes.
> Come to think of it, what happens on an out-of-order processor (e.g.
> Alpha EV6) when an instruction traps? Are preceding instructions 
> guaranteed to have completed? I'm curious.

Yes. All the instructions before hand are committed, and all
of the in-flight instruction after are aborted.
r~