how does primary core start secondary core on pi5 baremetal

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keep-beyond: Posts: 4; Joined: Fri Nov 21, 2025 2:53 pm

how does primary core start secondary core on pi5 baremetal

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Fri Nov 21, 2025 3:19 pm

I'm using raspberry pi 5b for FreeRTOS SMP porting. So far I can run FreeRTOS on single core. When I try to porting on multi cores, I found the first step is hard to go. As I don't know how to start the secondary core.
I find in the .dtsi of bcm2712 the secondary cores are started by PSCI smc, then I tried as follows:

Code: Select all

 ldr x0, =0x84000000
 dmb ish
 isb
 smc #0

then print the returned value x0 as version 1.1. It turns out the PSCI is supported. But when I tried to make CPU1 ON:

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 ldr x0, =0x84000003
 mov x1, #1
 adrp x2, _start
 add x2, x2, :lo12:_start
 mov x3, #0
 dmb ish
 isb
 smc #0

then I got -4, ALREADY ON.

I searched some info, it might because EEPROM bootloader + default armstub(PSCI/TF-A) already pull the others CPUs on. I have no chance to make it on again. I also modified the config.txt by adding kernel_old=1, auto_initramfs=0, and changed my linker script to allocate the _start to 0x0 rather than 0x80000, etc. But all failed, and I got muddled, is this way possible on pi5 or I'm making wrong, can anyone help me?

roliver: Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator; Posts: 58; Joined: Thu Sep 27, 2012 10:10 am

Re: how does primary core start secondary core on pi5 baremetal

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Mon Nov 24, 2025 8:52 am

Circle (a bare-metal project targetting Raspberry Pi) has support for multi-core on Pi5; that might be a decent starting point:
https://github.com/rsta2/circle/blob/7f ... p64.S#L101

keep-beyond: Posts: 4; Joined: Fri Nov 21, 2025 2:53 pm

Re: how does primary core start secondary core on pi5 baremetal

Quote

Thu Nov 27, 2025 1:58 am

roliver wrote: ↑
Mon Nov 24, 2025 8:52 am
Circle (a bare-metal project targetting Raspberry Pi) has support for multi-core on Pi5; that might be a decent starting point:
https://github.com/rsta2/circle/blob/7f ... p64.S#L101

Hi roliver, thanks for linking me to circle, it's very professional.
I have also found some ways in TF-A by writing the mailbox and send event waking up the secondary cores. Or by writing own armstub with the magic values.

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#define PLAT_RPI3_TM_ENTRYPOINT 0x100
#define PLAT_RPI3_TM_ENTRYPOINT_SIZE 8ULL
/* Hold entries for each CPU. */
#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + PLAT_RPI3_TM_ENTRYPOINT_SIZE)
#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE 8ULL
#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT)
#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + PLAT_RPI3_TM_HOLD_SIZE)
#define PLAT_RPI3_TM_HOLD_STATE_WAIT 0ULL
#define PLAT_RPI3_TM_HOLD_STATE_GO 1ULL
#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF 2ULL

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 mov x0, PLAT_RPI3_TM_HOLD_BASE
 add x0, x0, #8
 mov x1, PLAT_RPI3_TM_HOLD_STATE_GO
 str x1, [x0]
 isb
 mov x0, PLAT_RPI3_TM_ENTRYPOINT
 ldr x1, =_start
 str x1, [x0]
 isb
 sev