scan register
<electronics, testing >
A digital logic circuit which can act either as a flip-flop or as a serial shift register and which is used to form a scan path for testing. The most common design is a multiplexed flip-flop:
_ __ normal in --| \ | | |mux |------|D Q|---- normal/scan scan in ----|___/ | | output | |flip| test mode ----+ |flop| | | clk --------------------|> | |____|The addition of a multiplexor (mux) to each flip-flop's input allows operation in either normal or test mode. The output of each flip-flop goes to the normal functional logic as well as to the scan input of the next multiplexor in the scan path. The other common design is level-sensitive scan design (LSSD).
Last updated: 2011年12月16日
Nearby terms:
scanner ♦ scanno ♦ scan path ♦ scan register ♦ scar tissue code ♦ SCC ♦ SCCS
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