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10 June 2026
- diff hist CPU cache 00:46 +1 Guy Harris talk contribs (→{{Anchor|ICACHE|DCACHE|instruction cache|data cache}}Overview: L1 caches are usually split into separate I- and D-caches.)
- diff hist CPU cache 00:45 +49 Guy Harris talk contribs (→{{Anchor|ICACHE|DCACHE|instruction cache|data cache}}Overview: No need for lists under I-cache or D-cache; do them similarly to the TLB, and link to micro-operation cache and branch target instruction cache in the text as specialized I-caches (a branch target instruction cache is more like an I-cache than a branch target buffer is, as the latter redirects to branch target predictor). The higher-level caches cache both instruction and data fetches.)