ETRAX CRIS
The ETRAX CRIS is a RISC ISA and series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993.[1] The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token Ring support has been taken out from the latest chips as it has become obsolete.
Types of chips
[edit ]The CGA-1 (Coax Gate Array) was the first microprocessor developed by Axis Communications. It contains IBM 3270 (coax) and IBM 5250 (Twinax) communications. The chip has a microcontroller and various I/O's such as serial and parallel. The CGA-1 chip was designed by Martin Gren and Staffan Göransson.[2]
ETRAX
[edit ]- In 1993, Axis developed the ETRAX-1 Ethernet Controller, which has 10 Mbit/s Ethernet and Token Ring controllers.
- In 1995, Axis introduced the ETRAX-4 SoC which contains a Ethernet Controller, CPU, Memory Interface, SCSI controller, and parallel and serial I/O. [3]
- In 1997, Axis introduced the ETRAX 100 SoC which features a 10/100 Mbit/s Ethernet Controller, ATA controller, and Wide SCSI controller. The chip introduced on-chip unified instruction and data cache along with direct memory access.[4]
ETRAX 100LX
[edit ]In 2000, Axis Introduced the ETRAX 100LX SoC which features a MMU, USB controller, and SDRAM interface. The CPU is capable of 100 MIPS. The chip is able to run the Linux kernel without modifications except for low-level support.[5] The chip's maximum TDP is 0.35 Watts. As of Linux kernel 4.17, the architecture has been dropped due to being obsolete.[6]
Specifications:
- 32-bit RISC CPU core
- 10/100 Mbit/s Ethernet controller
- 4 asynchronous serial ports
- 2 synchronous serial ports
- 2 USB ports
- 2 Parallel ports
- 4 ATA (IDE) ports
- 2 Narrow SCSI ports (or 1 Wide)
- Support for SDRAM, Flash, EEPROM, SRAM
ETRAX 100LX MCM
[edit ]The ETRAX 100LX MCM is based on the ETRAX 100 LX. The chip has internal flash memory, SDRAM, and an Ethernet PHYceiver. The Chip can come with 2 MB flash and 8 MB SDRAM or 4 MB flash and 16 MB SDRAM.
ETRAX FS
[edit ]Introduced in 2005 with full Linux 2.6 support, the chip features:
ARTPEC
[edit ]The Axis Real-Time Picture Encoder Chip (ARTPEC) is a system on a chip (SoC) developed by Axis Communications.[7] There are currently nine generations of the chip, all of which run AXIS OS, a modified version of Linux designed for embedded devices. Not all products developed by Axis Communications use its custom chip. The chip is typically found in high-performance devices such as higher-end cameras, while lower-cost devices use SoCs from Ambarella.[8]
| Release year | Name | CPU | Features |
|---|---|---|---|
| 1999 | ARTPEC-1 | ETRAX CRIS |
Runs μClinux, an embedded operating system which became known as Embedded Linux |
| 2003 | ARTPEC-2 | ETRAX CRIS |
Combined digital signal processor and CPU into one package Hardware accelerated MPEG-4 video encoding |
| 2007 | ARTPEC-3 | ETRAX CRIS |
Hardware accelerated H.264 video encoding Capable of capturing 1080P video at 30 frames per second |
| 2011 | ARTPEC-4 | Multi-threaded MIPS CPU (34Kc)[9] |
Implements Lightfinder, a technology that allows a camera to see color in low light or challenging light conditions |
| 2013 | ARTPEC-5 | Dual-core MIPS CPU (1004Kf) |
Implements Forensic Capture, a High Dynamic Range technology that increases forensic details in a scene Implements Video encoders that utilize a technology called Zipstream to reduce bandwidth while maintaining video quality and detail |
| 2017 | ARTPEC-6 | ARM Cortex-A9 |
Can run video analytics capable of identifying objects such as humans and cars Capable of capturing 4K video at 30 frames per second |
| 2019 | ARTPEC-7 | ARM Cortex-A9 |
Implements a machine learning processor[10] Hardware accelerated H.265 video encoding Implements secure boot, which prevents booting of unauthorized firmware Improves low-light imaging via a technology called Lightfinder 2.0 |
| 2021 | ARTPEC-8 | ARM Cortex-A53 |
Implements a deep learning processor[11] Can run video analytics that recognize various object characteristics such as clothing |
| 2024 | ARTPEC-9 | ARM Cortex-A55 |
Hardware accelerated AV1 video encoding Faster deep learning processor capable of identifying more object characteristics |
References
[edit ]- ↑ axis.com - Axis Chip Development History Archived May 30, 2010, at the Wayback Machine
- ↑ "30 years of milestones" (PDF). Axis Communications.
- ↑ Zander, Per. "Axis Communications - A World Of Intelligent Networks" (PDF).
- ↑ "ETRAX 100: technical specifications". 1999年01月01日. Archived from the original on 2000年10月17日.
- ↑ The linux kernel source-code under /arch/cris contained the low-level CPU-specific additions required to make the Linux kernel able to run on the ETRAX/Cris CPUs. (See for example https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/cris?h=v4.13-rc4)
- ↑ "Linux-Kernel Archive: [PATCH 00/16] remove eight obsolete architectures".
- ↑ Viklund, Lars. "Introduction to Hardware Verification" (PDF).
- ↑ Ace, Ethan (August 30, 2019). "How To See If Your Camera Uses Huawei Hisilicon Chips". IPVM. Retrieved July 23, 2022.
- ↑ "Axis uses MIPS32 34Kc processor in video cameras". automation.com. Retrieved September 22, 2023.
- ↑ Jakobsson, Anton. "Distributing a Neural Network on Axis Cameras".
- ↑ Griffin, Joel (September 27, 2021). "Axis debuts next gen SoC during GSX". SecurityInfoWatch. Retrieved June 8, 2022.