MIC-1🔗 i

1MIC-1 Description🔗 i

The MIC-1 is a CPU with 16 general purpose 16-bit registers. Registers 5, 6, 7, 8, and 9 have default values 0000000000000000, 0000000000000001, 1111111111111111, 0000111111111111, and 0000000011111111 respectively.

It runs a single 256-instruction microprogram embedded in a control store ROM. Its ALU supports addition, bitwise AND, and bitwise negation. The ALU outputs flags for whether its result was negative or zero. The ALU is connected to a 1-bit shifter that can shift left, right, or not at all.

Its memory interface is two flags (one for reading, one for writing) as well as two 16-bit registers for interfacing with memory (the MAR–Memory Address Register–and MBR–Memory Buffer Register.) The top 4 bits of the MAR is ignored, so the MIC-1 has a 12-bit address space. Memory access is delayed by one cycle, during which the appropriate flag must be asserted. If both flags are asserted, then the external controller halts the machine.

The ALU’s A side is either a register or the MBR. The shifter result may be output to the MBR or any register. The MAR may be written from the ALU’s B side.

The top four words of memory (4092-4095) are wired to a UART. The first two connect to the receiver and the second two connect to the transmitter. The first of each holds an 8-bit character to be outputed in the bottom 8 bits. The second of each holds a 4 bit control flag in its lowest bits. The control bits are (from most to least significant): On, Interrupt, Done, Busy. The control bits are initialized to all zero. If the microprogram sets the On bit, then the component is enabled and stabilizes. The receiver stabilizes to not Done and Busy, while the transmitter stabilizes to Done and not Busy. When the receiver receives a character, it switches to Done and not Busy until the character is read by the CPU. When the program writes a character to the transmit buffer while the transmitter is On, then the transmitter switches to not Done and Busy, until the transmission is finished. The Interrupt flag is currently ignored by both components.

2 mic1 simulator🔗 i

raco mic1 ‹option› ... ‹microcode-path›‹memory-image-path› simulates the execution of the MIC-1.

‹microcode-path› must be a path to a file. If the extension is .prom, then it must be in the Microcode Image format. If the extension is .mc, then it must be in the MAL microcode language format and it will be compiled before loading.

‹memory-image-path› must be a path to a file. If the extension is .o, then it must be in the Memory Image format. If the extension is .s, then it must be in the MAC-1 macro-assembly format and it will be compiled before loading.

It accepts the following ‹option›s:

• --ll — simulates at the NAND gate level via compilation to a C program using cc.

• --lli — simulates at the NAND gate level via an interpreter.

• --hl — simulates at a high-level (default)

• --pc ‹pc-str› — specifies the initial value of the register 0, the Program Counter (default: 0)

• --sp ‹sp-str› — specifies the initial value of the register 2, the Stack Pointer (default: 1024)

3 mcc microcode compiler🔗 i

raco mcc ‹microcode-path› compiles MAL microcode language into the Microcode Image format.

‹microcode-path› must be a path to a file in the MAL microcode language format. raco mcc replaces the extension of this path with .prom and writes the corresponding Microcode Image.

4 masm macroassembler🔗 i

raco masm ‹asm-path› compiles MAC-1 macro-assembly into the Memory Image format.

‹asm-path› must be a path to a file in the MAC-1 macro-assembly format. raco masm replaces the extension of this path with .o and writes the corresponding Memory Image.

5HDL - General Purpose Hardware Description Language🔗 i

The implementation contains a general purpose hardware description language that compiles circuits to networks of NAND gates. The network can be simulated in Racket or via C compilation. In the future it may be documented.