In contrast to complete vertical integration of architecting, designing, manufacturing, assembling, and testing chips all within a single organization, an organization can choose to simply architect and design a chip before outsourcing the rest of the process to OSAT entities (e.g., external foundries and test houses). In the latter example, the device enters an OSAT facility in a much more vulnerable pre-production stage where many debug and test modes are accessible. Therefore, the chipmaker must place a certain level of trust with the OSAT. To counter this, the chipmaker often requires the OSAT partner to enter into restrictive non-disclosure agreements (NDAs). Nonetheless, OSAT vendors likely have many customers, which increases the risk of accidental sharing of information. There may also be a security vulnerability in the information technology (IT) system of the OSAT facility. Alternatively, a malicious insider at the OSAT facility may carry out an insider attack. Considering these factors, it behooves the chipmaker to minimize any confidential information in the device that may be accessible to the OSAT vendor.
Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could provide improper authorization to sensitive information.
| Impact | Details |
|---|---|
|
Gain Privileges or Assume Identity; Bypass Protection Mechanism; Execute Unauthorized Code or Commands; Modify Memory; Modify Files or Directories |
Scope: Confidentiality, Integrity, Access Control, Authentication, Authorization, Availability, Accountability, Non-Repudiation
Likelihood: Medium
The impact depends on the confidential information itself and who is inadvertently granted access. For example, if the confidential information is a key that can unlock all the parts of a generation, the impact could be severe.
|
| Phase(s) | Mitigation |
|---|---|
|
Architecture and Design |
Effectiveness: Moderate |
| Nature | Type | ID | Name |
|---|---|---|---|
| ChildOf | Class Class - a weakness that is described in a very abstract fashion, typically independent of any specific language or technology. More specific than a Pillar Weakness, but more general than a Base Weakness. Class level weaknesses typically describe issues in terms of 1 or 2 of the following dimensions: behavior, property, and resource. | 285 | Improper Authorization |
| Nature | Type | ID | Name |
|---|---|---|---|
| MemberOf | Category Category - a CWE entry that contains a set of other entries that share a common characteristic. | 1195 | Manufacturing and Life Cycle Management Concerns |
| Phase | Note |
|---|---|
| Implementation |
Verilog (Undetermined Prevalence)
VHDL (Undetermined Prevalence)
Class: Not Language-Specific (Undetermined Prevalence)
Class: Not OS-Specific (Undetermined Prevalence)
Class: Not Architecture-Specific (Undetermined Prevalence)
Processor Hardware (Undetermined Prevalence)
Class: Not Technology-Specific (Undetermined Prevalence)
Example 1
The following example shows how an attacker can take advantage of a piece of confidential information that has not been protected from the OSAT.
Suppose the preproduction device contains NVM (a storage medium that by definition/design can retain its data without power), and this NVM contains a key that can unlock all the parts for that generation. An OSAT facility accidentally leaks the key.
Compromising a key that can unlock all the parts of a generation can be devastating to a chipmaker.
The likelihood of such a compromise can be reduced by ensuring all memories on the preproduction device are properly scrubbed.
| Method | Details |
|---|---|
|
Architecture or Design Review |
Appropriate Post-Si tests should be carried out to ensure that residual confidential information is not left on parts leaving one facility for another facility.
Effectiveness: High |
|
Dynamic Analysis with Manual Results Interpretation |
Appropriate Post-Si tests should be carried out to ensure that residual confidential information is not left on parts leaving one facility for another facility.
Effectiveness: Moderate |
| Nature | Type | ID | Name |
|---|---|---|---|
| MemberOf | CategoryCategory - a CWE entry that contains a set of other entries that share a common characteristic. | 1396 | Comprehensive Categorization: Access Control |
Rationale
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.Comments
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.Maintenance
Maintenance
| Submissions | ||
|---|---|---|
| Submission Date | Submitter | Organization |
|
2020年05月29日
(CWE 4.2, 2020年08月20日) |
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna | Intel Corporation |
| Modifications | ||
| Modification Date | Modifier | Organization |
| 2023年06月29日 | CWE Content Team | MITRE |
| updated Mapping_Notes | ||
| 2023年04月27日 | CWE Content Team | MITRE |
| updated References, Relationships | ||
| 2023年01月31日 | CWE Content Team | MITRE |
| updated Maintenance_Notes | ||
| 2022年06月28日 | CWE Content Team | MITRE |
| updated Applicable_Platforms | ||
| 2022年04月28日 | CWE Content Team | MITRE |
| updated Applicable_Platforms | ||
| 2021年07月20日 | CWE Content Team | MITRE |
| updated Related_Attack_Patterns | ||
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