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Note that some of the commands below may be specific to GNU Make - you haven't said what tools you're using (although I guess you're on Windows since you mention .obj files).

Rules and object files

Currently, you have $(RESULT): $(SRCS), so it has to re-run your whole (single) compile line every time anything in $(SRCS) changes. Cacheing the compiler output for each individual file can indeed save time here:

$(OBJS) = $(patsubst %.cc, %.obj, $(SRCS))
$(RESULT): $(OBJS)
 $(CC) $(LIBS) $(OPT) $(INCLUDE) -o $@ $^

would do this (it just links all the .obj files to form your executable).

Now you need to tell make how to build those .obj files, which you can either leave up to the implicit rule (setting CXXFLAGS appropriately) or explicitly with:

%.obj : %.cc
 $(CC) $(OPT) $(INCLUDE) -c -o $@ $^

Directory structure

Note that leaving your build objects and output data inside your project tree isn't ideal - specifically it can add noise to whatever SCM tool you use, risks adding .obj files to source code control, which you almost certainly don't want, and makes it generally harder than necessary to clean your source tree.

You can use the patsubst command to change the path as well as the suffix of your object files, eg.

$(OBJS) = $(patsubst src/%.cc, build/%.obj, $(SRCS))

Dependencies

One major thing you're missing is header file dependencies: if you change a .h file, your makefile should be able to figure out which .o files need re-building. I don't know your toolchain, but for example gcc can automate this.

Note that some of the commands below may be specific to GNU Make - you haven't said what tools you're using (although I guess you're on Windows since you mention .obj files).

Rules and object files

Currently, you have $(RESULT): $(SRCS), so it has to re-run your whole (single) compile line every time anything in $(SRCS) changes. Cacheing the compiler output for each individual file can indeed save time here:

$(OBJS) = $(patsubst %.cc, %.obj, $(SRCS))
$(RESULT): $(OBJS)
 $(CC) $(LIBS) $(OPT) $(INCLUDE) -o $@ $^

would do this (it just links all the .obj files to form your executable).

Now you need to tell make how to build those .obj files, which you can either leave up to the implicit rule (setting CXXFLAGS appropriately) or explicitly with:

%.obj : %.cc
 $(CC) $(OPT) $(INCLUDE) -c -o $@ $^

Directory structure

Note that leaving your build objects and output data inside your project tree isn't ideal - specifically it can add noise to whatever SCM tool you use, risks adding .obj files to source code control, which you almost certainly don't want, and makes it generally harder than necessary to clean your source tree.

You can use the patsubst command to change the path as well as the suffix of your object files, eg.

$(OBJS) = $(patsubst src/%.cc, build/%.obj, $(SRCS))

Dependencies

One major thing you're missing is header file dependencies: if you change a .h file, your makefile should be able to figure out which .o files need re-building. I don't know your toolchain, but for example gcc can automate this.

Currently, you have $(RESULT): $(SRCS), so it has to re-run your whole (single) compile line every time anything in $(SRCS) changes. Cacheing the compiler output for each individual file can indeed save time here:

$(OBJS) = $(patsubst %.cc, %.obj, $(SRCS))
$(RESULT): $(OBJS)
 $(CC) $(LIBS) $(OPT) $(INCLUDE) -o $@ $^

would do this (it just links all the .obj files to form your executable).

Now you need to tell make how to build those .obj files, which you can either leave up to the implicit rule (setting CXXFLAGS appropriately) or explicitly with:

%.obj : %.cc
 $(CC) $(OPT) $(INCLUDE) -c -o $@ $^

Note that I'm leaving your build objects inside your project tree here, which isn't always ideal - you can use the patsubst to change the path as well as the suffix of your object files, eg.

$(OBJS) = $(patsubst src/%.cc, build/%.obj, $(SRCS))

or whatever.

One major thing you're missing is header file dependencies: if you change a .h file, your makefile should be able to figure out which .o files need re-building. I guess you're on windows and I don't know the toolchain, but for example gcc can automate this.

Note that some of the commands below may be specific to GNU Make - you haven't said what tools you're using (although I guess you're on Windows since you mention .obj files).

Rules and object files

Currently, you have $(RESULT): $(SRCS), so it has to re-run your whole (single) compile line every time anything in $(SRCS) changes. Cacheing the compiler output for each individual file can indeed save time here:

$(OBJS) = $(patsubst %.cc, %.obj, $(SRCS))
$(RESULT): $(OBJS)
 $(CC) $(LIBS) $(OPT) $(INCLUDE) -o $@ $^

would do this (it just links all the .obj files to form your executable).

Now you need to tell make how to build those .obj files, which you can either leave up to the implicit rule (setting CXXFLAGS appropriately) or explicitly with:

%.obj : %.cc
 $(CC) $(OPT) $(INCLUDE) -c -o $@ $^

Directory structure

Note that leaving your build objects and output data inside your project tree isn't ideal - specifically it can add noise to whatever SCM tool you use, risks adding .obj files to source code control, which you almost certainly don't want, and makes it generally harder than necessary to clean your source tree.

You can use the patsubst command to change the path as well as the suffix of your object files, eg.

$(OBJS) = $(patsubst src/%.cc, build/%.obj, $(SRCS))

Dependencies

One major thing you're missing is header file dependencies: if you change a .h file, your makefile should be able to figure out which .o files need re-building. I don't know your toolchain, but for example gcc can automate this.