Luca Fehlings fehlings · he/him
  • München, Germany
  • https://fehlings.github.io

  • Engineer working on memory devices & circuits. Currently PostDoc @ Technical University of Munich

  • Joined on 2023年04月01日
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Boilerplate code to create matplotlib-based publication-ready plots
Updated 2026年04月13日 16:04:58 +02:00
VACASK is a Verilog-A Circuit Analysis Kernel - an analog circuit simulator with a device library built from Verilog-A modules
Updated 2026年01月28日 14:20:56 +01:00