An attempt to continue developing the ch32vx led to the problem of adding two HART devices, such as the ch32h417. The ability to unified describe vendor SCRs was also made possible.
Below is the GDB log when connecting WlinkE to ch32h417, bmpa
klen@klen-dev:~$ riscv32-kgp-elf-gdb -ex "tar ext :2000" -ex "mon a" -ex "set width 0" -ex "set pagination off" -q
Remote debugging using :2000
Target voltage: Unknown
JTAG scan found no devices.
SWD scan found no devices.
Available Targets:
No. Att Driver
1 ch32h417qeu6 qkv3f rv32imafcb
2 ch32h417qeu6 qkv5f rv32imafcb
(gdb) att 2
Attaching to Remote target
⚠️ warning: No executable has been specified and target does not support
determining executable automatically. Try using the "file" command.
[Switching to thread 1 (Thread 1)]
0x0000027a in ?? ()
(gdb) info all
zero 0x0 0
ra 0x27a 0x27a
sp 0x2017fff0 0x2017fff0
gp 0x20100800 0x20100800
tp 0xfbf38cd4 0xfbf38cd4
t0 0x0 0
t1 0x8ab939da -1967572518
t2 0x8ab939da -1967572518
fp 0x50040fe4 0x50040fe4
s1 0x22222222 572662306
a0 0x8ab939da -1967572518
a1 0x455c 17756
a2 0x8ab97c86 -1967555450
a3 0xc58279da -981304870
a4 0x40011000 1073811456
a5 0x8 8
a6 0x8ab97c86 -1967555450
a7 0x8ab97c86 -1967555450
s2 0x9c737dbf -1670152769
s3 0x472ee72f 1194256175
s4 0xf9214bdf -115258401
s5 0x2befa93e 737126718
s6 0xa7454b7d -1488630915
s7 0x35bdfe74 901643892
s8 0x48546dec 1213492716
s9 0x60ffc7ef 1627375599
s10 0x3238367e 842544766
s11 0x391ebe3b 958316091
t3 0x572f90c0 1462735040
t4 0xdd96ec46 -577311674
t5 0xc 12
t6 0xf000 61440
pc 0x27a 0x27a
ft0 2112694335 (raw 0x7ded283f)
ft1 -1496617181 (raw 0xa6cb6f23)
ft2 -315419612 (raw 0xed331424)
ft3 1130313222 (raw 0x435f3606)
ft4 -919836379 (raw 0xc92c6925)
ft5 -721978524 (raw 0xd4f77b64)
ft6 -926296584 (raw 0xc8c9d5f8)
ft7 415006111 (raw 0x18bc7d9f)
fs0 -1212093609 (raw 0xb7c0eb57)
fs1 656770457 (raw 0x27258599)
fa0 1341521003 (raw 0x4ff5fc6b)
fa1 -1988975300 (raw 0x8972a53c)
fa2 1589444096 (raw 0x5ebcfe00)
fa3 -427792658 (raw 0xe68066ee)
fa4 1994172369 (raw 0x76dca7d1)
fa5 1866081681 (raw 0x6f3a2591)
fa6 2093393342 (raw 0x7cc6a5be)
fa7 1046834467 (raw 0x3e656d23)
fs2 -2115692866 (raw 0x81e516be)
fs3 -438113305 (raw 0xe5e2ebe7)
fs4 1659122110 (raw 0x62e431be)
fs5 -1418041717 (raw 0xab7a668b)
fs6 -1139450422 (raw 0xbc155dca)
fs7 -137003090 (raw 0xf7d57fae)
fs8 2147482613 (raw 0x7ffffbf5)
fs9 -15206445 (raw 0xff17f7d3)
fs10 -129243577 (raw 0xf84be647)
fs11 -741475426 (raw 0xd3cdfb9e)
ft8 1044451294 (raw 0x3e410fde)
ft9 1388846927 (raw 0x52c81f4f)
ft10 -647073632 (raw 0xd96e70a0)
ft11 1566758132 (raw 0x5d62d4f4)
fflags 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x0 FRM:0 [RNE (round to nearest; ties to even)]
fcsr 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:0 [RNE (round to nearest; ties to even)]
mstatus 0x2008 SD:0 VM:00 MXR:0 PUM:0 MPRV:0 XS:0 FS:1 MPP:0 HPP:0 SPP:0 MPIE:0 HPIE:0 SPIE:0 UPIE:0 MIE:1 HIE:0 SIE:0 UIE:0
misa 0x40901127 RV32ABCFIMUX
mie 0x101 257
mtvec 0x3 0x3
mscratch 0x72795b21 0x72795b21
mepc 0xd679ef70 0xd679ef70
mcause 0xeb 235
mtval 0x5b6aca88 1533725320
pmpcfg0 0x0 [ cfg0_read=denide cfg0_write=denide cfg0_executable=denide cfg0_address_alignment=off cfg0_lock=disable cfg1_read=denide cfg1_write=denide cfg1_executable=denide cfg1_address_alignment=off cfg1_lock=disable cfg2_read=denide cfg2_write=denide cfg2_executable=denide cfg2_address_alignment=off cfg2_lock=disable cfg3_read=denide cfg3_write=denide cfg3_executable=denide cfg3_address_alignment=off cfg3_lock=disable ]
pmpaddr0 0x2cdfaa35 0x2cdfaa35
pmpaddr1 0x2a5197a3 0x2a5197a3
pmpaddr2 0x277d7f5d 0x277d7f5d
pmpaddr3 0x227e87f9 0x227e87f9
tselect 0x3 3
tdata1 0x20000048 536870984
tdata2 0x0 0
tinfo 0x4 4
dcsr 0x400080c0 1073774784
dpc 0x27a 634
dscratch0 0x50040fe4 1342443492
dscratch1 0x8ab939da -1967572518
mcycle 0x7fc04ca1 2143308961
minstret 0x3b9c4f16 1000099606
mvendorid 0x0 0
marchid 0xdc68d8ae [ vendor0=w vendor1=c vendor2=h arch=v ser=5 ver=n ]
mimpid 0xdc688001 [ vendor0=w vendor1=c vendor2=h minor=1 ]
mhartid 0x1 1
mcount_inhibit 0x0 0
dbgmcu0 0x0 0
ucycle 0x801d4c51 -2145563567
uinstret 0x3bb02b1a 1001401114
cstrcr 0xf000003 251658243
cpmpocr 0x0 0
hw_popdm 0x200c0000 537657344
memary 0x600f0fff 1611599871
tcm_rrduty 0x0 0
cmcr 0x0 0
meminfo 0x120a0030 [ dtcm_datasize=256kb dtcm_linesize=32byte itcm_datasize=128kb itcm_linesize=32byte icache_way=2-way icache_datasize=32kb icache_linesize=8byte ]
gintenr 0x2008 8200
intsyscr 0xb 11
corecfgr 0x0 0
inestcr 0x0 0
(gdb) info mem
Using memory regions provided by the target.
Num Enb Low Addr High Addr Attrs
0 y 0x200a0000 0x200c0000 rw nocache
1 y 0x200c0000 0x20100000 rw nocache
2 y 0x20100000 0x20180000 rw nocache
3 y 0x50040000 0x50041000 rw nocache
(gdb)
blacmagic log:
klen@klen-dev:~$ blackmagic -v1
Black Magic Debug App v2.0.0-616-gbc864aad-dirty
for Black Magic Probe, ST-Link v2 and v3, CMSIS-DAP, J-Link, FTDI (MPSSE) and WCH-Link
Using 1a86:8010 6B0D8F06F104 wch.cn
WCH-Link ---
Firmware version: v2.21
Hardware type: WCH-LinkE (CH32V305)
Setting V6ONLY to off for dual stack listening.
Listening on TCP port: 2000
Got connection
Setting max debug interface frequency not available or not yet implemented
Reading max debug interface frequency not available or not yet implemented
Setting max debug interface frequency not available or not yet implemented
Reading max debug interface frequency not available or not yet implemented
WCH-Link attached to RISC-V chip: Unknown
ID code: 0x4170052d
RISC-V non-standard DMI, proceeding anyway
RISC-V debug v0.13 DM
Hart has 2 data registers and 8 progbuf registers
Attempting 64-bit read on misa
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
Attempting 32-bit read on misa
Hart 0: 32-bit RISC-V (arch = dc68d866), rv32imafcb ISA (exts = 00901127), vendor = 0, impl = dc688002
Hart has 4 trigger slots available
-> riscv32_probe
ch32vx idcode: 0x4170052d
ch32vx flash size: 960Kb
Hart has 2 data registers and 8 progbuf registers
Attempting 64-bit read on misa
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
Attempting 32-bit read on misa
Hart 1: 32-bit RISC-V (arch = dc68d8ae), rv32imafcb ISA (exts = 00901127), vendor = 0, impl = dc688001
Hart has 4 trigger slots available
-> riscv32_probe
ch32vx idcode: 0x4170052d
ch32vx flash size: 960Kb
devices were added to the description (src/target/ch32vx.c)
static const struct ch32vx_descr_t ch32vx_descrs[] =
{
{ 0x00300500, ch32v003f4p6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00310500, ch32v003f4u6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00320500, ch32v003a4m6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00330500, ch32v003j4m6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f6p6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f8p6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f8u6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203g6u6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203g8r6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203k8t6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203c6t6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
{ 0x20310500, ch32v203c8t6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203c8u6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203rbt6_harts, ch32h203xb_ram, ch32h203xb_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205cct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205rct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205vct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
{ 0x30330504, ch32v303cbt6_harts, ch32h303xb_ram, ch32h303xb_flash, ch32vx_cmd_list },
{ 0x30320504, ch32v303rbt6_harts, ch32h303xb_ram, ch32h303xb_flash, ch32vx_cmd_list },
{ 0x30310504, ch32v303rct6_harts, ch32h303xc_ram, ch32h303xc_flash, ch32vx_cmd_list },
{ 0x30300504, ch32v303vct6_harts, ch32h303xc_ram, ch32h303xc_flash, ch32vx_cmd_list },
{ 0x30520508, ch32v305fbp6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
// { 0x305?????, ch32v305gbu6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
// { 0x305?????, ch32v305cct6_harts, ch32h305xc_ram, ch32h305xc_flash, ch32vx_cmd_list },
{ 0x30500508, ch32v305cbt6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
{ 0x30730508, ch32v307rct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x30710508, ch32v307wcu6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x30700508, ch32v307vct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
// { 0x317?????, ch32v317wcu6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
// { 0x317?????, ch32v317vct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x4170050d, ch32h417qeu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417meu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417weu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417rdu6_harts, ch32h417_ram, ch32h417xd_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417reu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
} ;
The devices that are commented out are described but not added because I don't know their IDCODE's. The WCH documentation doesn't answer this question.
Please review my patch and give me feedback.
If my work seems promising, I can continue adding devices and participate in implementing FLASH management for programming support.
An attempt to continue developing the ch32vx led to the problem of adding two HART devices, such as the ch32h417. The ability to unified describe vendor SCRs was also made possible.
Below is the GDB log when connecting WlinkE to ch32h417, bmpa
```
klen@klen-dev:~$ riscv32-kgp-elf-gdb -ex "tar ext :2000" -ex "mon a" -ex "set width 0" -ex "set pagination off" -q
Remote debugging using :2000
Target voltage: Unknown
JTAG scan found no devices.
SWD scan found no devices.
Available Targets:
No. Att Driver
1 ch32h417qeu6 qkv3f rv32imafcb
2 ch32h417qeu6 qkv5f rv32imafcb
(gdb) att 2
Attaching to Remote target
⚠️ warning: No executable has been specified and target does not support
determining executable automatically. Try using the "file" command.
[Switching to thread 1 (Thread 1)]
0x0000027a in ?? ()
(gdb) info all
zero 0x0 0
ra 0x27a 0x27a
sp 0x2017fff0 0x2017fff0
gp 0x20100800 0x20100800
tp 0xfbf38cd4 0xfbf38cd4
t0 0x0 0
t1 0x8ab939da -1967572518
t2 0x8ab939da -1967572518
fp 0x50040fe4 0x50040fe4
s1 0x22222222 572662306
a0 0x8ab939da -1967572518
a1 0x455c 17756
a2 0x8ab97c86 -1967555450
a3 0xc58279da -981304870
a4 0x40011000 1073811456
a5 0x8 8
a6 0x8ab97c86 -1967555450
a7 0x8ab97c86 -1967555450
s2 0x9c737dbf -1670152769
s3 0x472ee72f 1194256175
s4 0xf9214bdf -115258401
s5 0x2befa93e 737126718
s6 0xa7454b7d -1488630915
s7 0x35bdfe74 901643892
s8 0x48546dec 1213492716
s9 0x60ffc7ef 1627375599
s10 0x3238367e 842544766
s11 0x391ebe3b 958316091
t3 0x572f90c0 1462735040
t4 0xdd96ec46 -577311674
t5 0xc 12
t6 0xf000 61440
pc 0x27a 0x27a
ft0 2112694335 (raw 0x7ded283f)
ft1 -1496617181 (raw 0xa6cb6f23)
ft2 -315419612 (raw 0xed331424)
ft3 1130313222 (raw 0x435f3606)
ft4 -919836379 (raw 0xc92c6925)
ft5 -721978524 (raw 0xd4f77b64)
ft6 -926296584 (raw 0xc8c9d5f8)
ft7 415006111 (raw 0x18bc7d9f)
fs0 -1212093609 (raw 0xb7c0eb57)
fs1 656770457 (raw 0x27258599)
fa0 1341521003 (raw 0x4ff5fc6b)
fa1 -1988975300 (raw 0x8972a53c)
fa2 1589444096 (raw 0x5ebcfe00)
fa3 -427792658 (raw 0xe68066ee)
fa4 1994172369 (raw 0x76dca7d1)
fa5 1866081681 (raw 0x6f3a2591)
fa6 2093393342 (raw 0x7cc6a5be)
fa7 1046834467 (raw 0x3e656d23)
fs2 -2115692866 (raw 0x81e516be)
fs3 -438113305 (raw 0xe5e2ebe7)
fs4 1659122110 (raw 0x62e431be)
fs5 -1418041717 (raw 0xab7a668b)
fs6 -1139450422 (raw 0xbc155dca)
fs7 -137003090 (raw 0xf7d57fae)
fs8 2147482613 (raw 0x7ffffbf5)
fs9 -15206445 (raw 0xff17f7d3)
fs10 -129243577 (raw 0xf84be647)
fs11 -741475426 (raw 0xd3cdfb9e)
ft8 1044451294 (raw 0x3e410fde)
ft9 1388846927 (raw 0x52c81f4f)
ft10 -647073632 (raw 0xd96e70a0)
ft11 1566758132 (raw 0x5d62d4f4)
fflags 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0
frm 0x0 FRM:0 [RNE (round to nearest; ties to even)]
fcsr 0x0 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:0 [RNE (round to nearest; ties to even)]
mstatus 0x2008 SD:0 VM:00 MXR:0 PUM:0 MPRV:0 XS:0 FS:1 MPP:0 HPP:0 SPP:0 MPIE:0 HPIE:0 SPIE:0 UPIE:0 MIE:1 HIE:0 SIE:0 UIE:0
misa 0x40901127 RV32ABCFIMUX
mie 0x101 257
mtvec 0x3 0x3
mscratch 0x72795b21 0x72795b21
mepc 0xd679ef70 0xd679ef70
mcause 0xeb 235
mtval 0x5b6aca88 1533725320
pmpcfg0 0x0 [ cfg0_read=denide cfg0_write=denide cfg0_executable=denide cfg0_address_alignment=off cfg0_lock=disable cfg1_read=denide cfg1_write=denide cfg1_executable=denide cfg1_address_alignment=off cfg1_lock=disable cfg2_read=denide cfg2_write=denide cfg2_executable=denide cfg2_address_alignment=off cfg2_lock=disable cfg3_read=denide cfg3_write=denide cfg3_executable=denide cfg3_address_alignment=off cfg3_lock=disable ]
pmpaddr0 0x2cdfaa35 0x2cdfaa35
pmpaddr1 0x2a5197a3 0x2a5197a3
pmpaddr2 0x277d7f5d 0x277d7f5d
pmpaddr3 0x227e87f9 0x227e87f9
tselect 0x3 3
tdata1 0x20000048 536870984
tdata2 0x0 0
tinfo 0x4 4
dcsr 0x400080c0 1073774784
dpc 0x27a 634
dscratch0 0x50040fe4 1342443492
dscratch1 0x8ab939da -1967572518
mcycle 0x7fc04ca1 2143308961
minstret 0x3b9c4f16 1000099606
mvendorid 0x0 0
marchid 0xdc68d8ae [ vendor0=w vendor1=c vendor2=h arch=v ser=5 ver=n ]
mimpid 0xdc688001 [ vendor0=w vendor1=c vendor2=h minor=1 ]
mhartid 0x1 1
mcount_inhibit 0x0 0
dbgmcu0 0x0 0
ucycle 0x801d4c51 -2145563567
uinstret 0x3bb02b1a 1001401114
cstrcr 0xf000003 251658243
cpmpocr 0x0 0
hw_popdm 0x200c0000 537657344
memary 0x600f0fff 1611599871
tcm_rrduty 0x0 0
cmcr 0x0 0
meminfo 0x120a0030 [ dtcm_datasize=256kb dtcm_linesize=32byte itcm_datasize=128kb itcm_linesize=32byte icache_way=2-way icache_datasize=32kb icache_linesize=8byte ]
gintenr 0x2008 8200
intsyscr 0xb 11
corecfgr 0x0 0
inestcr 0x0 0
(gdb) info mem
Using memory regions provided by the target.
Num Enb Low Addr High Addr Attrs
0 y 0x200a0000 0x200c0000 rw nocache
1 y 0x200c0000 0x20100000 rw nocache
2 y 0x20100000 0x20180000 rw nocache
3 y 0x50040000 0x50041000 rw nocache
(gdb)
```
blacmagic log:
```
klen@klen-dev:~$ blackmagic -v1
Black Magic Debug App v2.0.0-616-gbc864aad-dirty
for Black Magic Probe, ST-Link v2 and v3, CMSIS-DAP, J-Link, FTDI (MPSSE) and WCH-Link
Using 1a86:8010 6B0D8F06F104 wch.cn
WCH-Link ---
Firmware version: v2.21
Hardware type: WCH-LinkE (CH32V305)
Setting V6ONLY to off for dual stack listening.
Listening on TCP port: 2000
Got connection
Setting max debug interface frequency not available or not yet implemented
Reading max debug interface frequency not available or not yet implemented
Setting max debug interface frequency not available or not yet implemented
Reading max debug interface frequency not available or not yet implemented
WCH-Link attached to RISC-V chip: Unknown
ID code: 0x4170052d
RISC-V non-standard DMI, proceeding anyway
RISC-V debug v0.13 DM
Hart has 2 data registers and 8 progbuf registers
Attempting 64-bit read on misa
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
Attempting 32-bit read on misa
Hart 0: 32-bit RISC-V (arch = dc68d866), rv32imafcb ISA (exts = 00901127), vendor = 0, impl = dc688002
Hart has 4 trigger slots available
-> riscv32_probe
ch32vx idcode: 0x4170052d
ch32vx flash size: 960Kb
Hart has 2 data registers and 8 progbuf registers
Attempting 64-bit read on misa
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
CSR access failed: 2
Attempting 32-bit read on misa
Hart 1: 32-bit RISC-V (arch = dc68d8ae), rv32imafcb ISA (exts = 00901127), vendor = 0, impl = dc688001
Hart has 4 trigger slots available
-> riscv32_probe
ch32vx idcode: 0x4170052d
ch32vx flash size: 960Kb
```
devices were added to the description (src/target/ch32vx.c)
```
static const struct ch32vx_descr_t ch32vx_descrs[] =
{
{ 0x00300500, ch32v003f4p6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00310500, ch32v003f4u6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00320500, ch32v003a4m6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
{ 0x00330500, ch32v003j4m6_harts, ch32v003_ram, ch32v003_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f6p6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f8p6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203f8u6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203g6u6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203g8r6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203k8t6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203c6t6_harts, ch32h203x6_ram, ch32h203x6_flash, ch32vx_cmd_list },
{ 0x20310500, ch32v203c8t6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203c8u6_harts, ch32h203x8_ram, ch32h203x8_flash, ch32vx_cmd_list },
// { 0x203?????, ch32v203rbt6_harts, ch32h203xb_ram, ch32h203xb_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205cct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205rct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
// { 0x205?????, ch32v205vct6_harts, ch32h205_ram, ch32h205_flash, ch32vx_cmd_list },
{ 0x30330504, ch32v303cbt6_harts, ch32h303xb_ram, ch32h303xb_flash, ch32vx_cmd_list },
{ 0x30320504, ch32v303rbt6_harts, ch32h303xb_ram, ch32h303xb_flash, ch32vx_cmd_list },
{ 0x30310504, ch32v303rct6_harts, ch32h303xc_ram, ch32h303xc_flash, ch32vx_cmd_list },
{ 0x30300504, ch32v303vct6_harts, ch32h303xc_ram, ch32h303xc_flash, ch32vx_cmd_list },
{ 0x30520508, ch32v305fbp6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
// { 0x305?????, ch32v305gbu6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
// { 0x305?????, ch32v305cct6_harts, ch32h305xc_ram, ch32h305xc_flash, ch32vx_cmd_list },
{ 0x30500508, ch32v305cbt6_harts, ch32h305xb_ram, ch32h305xb_flash, ch32vx_cmd_list },
{ 0x30730508, ch32v307rct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x30710508, ch32v307wcu6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x30700508, ch32v307vct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
// { 0x317?????, ch32v317wcu6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
// { 0x317?????, ch32v317vct6_harts, ch32h307_ram, ch32h307_flash, ch32vx_cmd_list },
{ 0x4170050d, ch32h417qeu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417meu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417weu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417rdu6_harts, ch32h417_ram, ch32h417xd_flash, ch32vx_cmd_list },
// { 0x417?????, ch32h417reu6_harts, ch32h417_ram, ch32h417xe_flash, ch32vx_cmd_list },
} ;
```
The devices that are commented out are described but not added because I don't know their IDCODE's. The WCH documentation doesn't answer this question.
Please review my patch and give me feedback.
If my work seems promising, I can continue adding devices and participate in implementing FLASH management for programming support.
5.5 KiB
44 KiB