内容説明
Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.
目次
Chapter 1: FPGA Overview: Architecture and CADChapter 2: Power Dissipation in Modern FPGAsChapter 3: Power Estimation in FPGAsChapter 4: Dynamic Power Reduction Techniques in FPGAsChapter 5: Leakage Power Reduction in FPGAs Using MTCMOS TechniquesChapter 6: Leakage Power Reduction in FPGAs Through Input Pin Reordering
「Nielsen BookData」 より