Message264018
| Author |
vstinner |
| Recipients |
Yury.Selivanov, casevh, josh.r, lemburg, mark.dickinson, pitrou, rhettinger, serhiy.storchaka, skrah, vstinner, yselivanov, zbyrne |
| Date |
2016年04月22日.14:05:45 |
| SpamBayes Score |
-1.0 |
| Marked as misclassified |
Yes |
| Message-id |
<1461333945.44.0.88161417026.issue21955@psf.upfronthosting.co.za> |
| In-reply-to |
| Content |
Maybe we should adopt a difference approach.
There is something called "inline caching": put the cache between instructions, in the same memory block. Example of paper on CPython:
"Efficient Inline Caching without Dynamic Translation" by Stefan Brunthaler (2009)
https://www.sba-research.org/wp-content/uploads/publications/sac10.pdf
Maybe we can build something on top of the issue #26219 "implement per-opcode cache in ceval"? |
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History
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| Date |
User |
Action |
Args |
| 2016年04月22日 14:05:46 | vstinner | set | recipients:
+ vstinner, lemburg, rhettinger, mark.dickinson, pitrou, casevh, skrah, Yury.Selivanov, serhiy.storchaka, yselivanov, josh.r, zbyrne |
| 2016年04月22日 14:05:45 | vstinner | set | messageid: <1461333945.44.0.88161417026.issue21955@psf.upfronthosting.co.za> |
| 2016年04月22日 14:05:45 | vstinner | link | issue21955 messages |
| 2016年04月22日 14:05:45 | vstinner | create |
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