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Timeline for Adjust time calculation after Timer0 frequency change

Current License: CC BY-SA 3.0

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Nov 20, 2017 at 8:49 comment added Lefteris @EdgarBonet Yes I've just read this. Thank you
Nov 20, 2017 at 8:46 comment added Edgar Bonet @Lefteris: Read the datasheet: "The Phase Correct PWM mode is based on dual-slope operation: The counter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM."
Nov 20, 2017 at 8:29 comment added Lefteris @EdgarBonet If I have understood correct, the TCTN0 register increases every CLK/64 tick. So it is only going up. It is reset every time it overflows and TIMER0_OVF_vect ISR is called. So still not understanding what phase correct PWM has to do with this.
Nov 20, 2017 at 8:25 comment added Lefteris Correction on the above, modulo was wrong, I'm dividing by 64 on the return function now: return ((m << 8) + (t/64) ) * (64 / clockCyclesPerMicrosecond()); Still the problem remains with delays function which I don't understand
Nov 20, 2017 at 8:23 comment added Edgar Bonet @Lefteris: The counter is going up and down because the OP configured it in "phase correct PWM" mode.
Nov 20, 2017 at 8:07 comment added Lefteris Since your counter is now going alternatively up and down Why is the TCNT0 going up or down? It's going up and every time it overflow the ISR is called. Am I missing something? I tried to solve this by increasing the timer0_overflow_count once every 64 times only, and on the micros() function return the time as return ((m << 8) + (t % 64)) * (64 / clockCyclesPerMicrosecond()); So I do a mod on the TCNT0 counter as my Timer is ticking 64 times faster. But although the micros() seem to be ok delay() is still running faster and I'm not understanding why...
Jul 17, 2015 at 8:51 comment added Splitframe Thanks for the sophisticated answer! At this point also thanks to @jakec for discussing the problem with me!
Jul 17, 2015 at 8:49 vote accept Splitframe
Jul 17, 2015 at 8:37 history answered Edgar Bonet CC BY-SA 3.0

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