Fundamentals of Analog/RF design: Noise, Signal, Power

Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed by an analog/RF circuit.

Transconductors

MOS Thermal Noise

Shown below is a disembodied MOS transconductor:

scan0085a

It takes an input voltage vi and outputs a current i_o. To avoid clipping, i_o would need to be less than I_D, the bias voltage on the MOS transistor. However, let’s say that for some linearity requirement (IM₂, IM₃, IM₅, etc.) that we limit i_o to be less than ×ばつI_D.

So, we know the signal power is:

P_sig = (×ばつI_D)² = ×ばつI_D^2

This power is computed as a current; we could equally have the transconductor drive a specified load impedance and compute all the quantities as voltage, but they will not change the end result.

Likewise, the noise current power is:

Pnoise = ×ばつk×ばつg_m×ばつB/3

At this point, it is useful to represent g_m in terms of voltage and current:

g_m = ×ばつI_D/V_DSat
→ P_noise = ×ばつk×ばつI_D×ばつB/(×ばつV_DSat)

Therefore:

SNR = P_sig/P_noise = ×ばつI_D×ばつV_DSat/(×ばつk×ばつB)

Note that the term I_D×ばつV_DSat is a lower-bound on the power dissipated across the FET. In fact, the actual power dissipated across the FET is I_D×ばつV_DS, which is actually greater than I_D×ばつV_DSat, since V_DS > V_DS to keep the FET in saturation.

To summarize:

1. For a given SNR, we need a certain I_D×ばつV_DSat product (P_min)
2. The actual power dissipated by the FET is greater than this I_D×ばつV_DSat product P_min
3. Therefore, the SNR dictates how much power we must dissipate

BJT Noise

A similar argument holds for the BJT. The difference is that the BJT’s are less sensitive to voltage, since due to their exponential current-voltage curve, the voltage varies very little:

scan0083a

P_noise = ×ばつk×ばつI_C/V_t

P_sig = ×ばつI_C^2

SNR = ×ばつI_C×ばつV_t/(×ばつk×ばつB)

Once again, this I_C×ばつV_t is a lower-bound on the noise dissipated across the BJT: V_BE > V_t and V_CE > V_BE → V_CE > V_t. The true power dissipated across the BJT is I_C×ばつV_CE which is greater than Pmin = I_C×ばつV_t, and to maintain a certain SNR, we have P_min = ×ばつk×ばつB/(α^2).

Loads

Resistor Noise

We now veer off into load country, considering resistor loads for our transconductor:

scan0084a

Considering only noise due to the resistor, and making the assumption that the signal current is once again limited to ×ばつI_D (where I_D = I_R):

P_noise = ×ばつk×ばつB/R = ×ばつk×ばつI_R/V_R

SNR = ×ばつI_R×ばつV_R/(×ばつk&Times×ばつB)

Note that this case is not general: in many cases, we don’t have to have I_R = I_D, so the P_sig has nothing to do with the resistor current. My intent is not to generalize to that much degree. I assume we have a transconductor–and every transconductor has to have a load (resistive, inductive, or active) that supplies dc current.

Active Loads

Going through the math, one finds that active loads (BJT or MOS) also follow a similar derivation: the noise contributed by the load is proportional to the current to minimum-voltage ratio of the load. Also, the signal current coming into the load is constrained by the load current, since that same load current flows through the transconductor:

MOS Load: P_noise = ×ばつk×ばつI_D×ばつB/(×ばつV_DSat) | P_sig = ×ばつI_D

BJT Load: P_noise = ×ばつk×ばつI_C/V_t | P_sig = ×ばつI_C

Final Note

One final note: many times circuit designers think that they need to maximize g_m of devices to minimize noise. This optimum is not always the case. Generally, for a transconductor, better gm yields better SNR (assuming linearity is not an issue). However, the g_m of a load makes it add more (current) noise without improving signal power. Therefore, for loads, one wants to minimize g_m.