• Discrete Cosine Transforms
• Hardware design
• Algorithms

Programmable fine-grain many-core architectures and circuits.

Computationally-intensive application development.

Programming tool development such as compilers, optimization, and mapping tools.

Complete deep-submicron CMOS chip designs.

Asynchronous Array of simple Processors (AsAP)

Many members of the VCL are participating in work on the circuits, functional units, architecture, interconnection network, algorithms, applications, and tools for a high-performance and energy-efficient processing system targeting computationally-demanding multi-algorithm DSP system applications. The single-chip processing system is comprised of a large number of fine-grain asynchronously-operating programmable processors connected by a reconfigurable 2-dimensional mesh network.

AsAP 1. The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the second highest clock rate processor designed in any university. Details of the chip were presented in the Technology and Architecture Directions session at ISSCC in Feb. 2006. See the paper below.

Also see the EE Times article "Asynchronous array of processors chip presented at ISSCC 2006," February 9, 2006.

AsAP 2. A second generation 65 nm CMOS design contains 167 processors with dedicated FFT, Viterbi, and video motion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect. The programmable processors can individually and dynamically change their supply voltage and clock frequency. The chip is fully-functional. Processors operate up to 1.2 GHz at 1.3 V which is believed to be the highest clock rate fabricated processor designed in any university. At 1.2 V, they operate at 1.07 GHz and 47 mW when 100% active. At 0.675 V, they operate at 66 MHz and 608 μW when 100% active. This operating point enables 1 trillion MAC or ALU ops/sec with a power dissipation of only 9.2 Watts. Due to its MIMD architecture and fine-grain clock oscillator stalling, this energy efficiency per operation is almost perfectly constant across widely varying workloads--which is not the case for many architectures.

The 1000-processor KiloCore architecture and chip is the third generation fine-grain many-core processor array developed by members of the VCL.

A fourth-generation fabricated chip with significantly increased performance has been fabricated but not yet fully tested or published.

Low Density Parity Check (LDPC) Decoders

We are working on LDPC algorithms, architectures, and circuits targeting several regimes, with a continual emphasis on high energy efficiency:
• Very high rate decoders
• Efficient decoding algorithms useful at many throughput rates

Special Purpose Processors

We are working on algorithms, architectures, and circuits for a number of dedicated purpose processing engines. Several active projects include:
• Fast Fourier Transform (FFT)
• Viterbi decoder
• H.264 and HEVC video encoding and decoding
• second generation video motion estimation and stabilization
• database record processing
• other accelerator architectures



Sponsors of Our Work

National Science Foundation
• CCF Grant No. 1321163
• CCF Grant No. 1018972
• REU Grant 2010
• CCF Grant No. 0903549
• CAREER award No. 0546907
• REU Grant 2005
• CCF Grant No. 0430090
• CCF Grant No. 0312837 (Co-PI) SRC, Semiconductor Research Corporation
• GRC Grant 2321.001
• GRC Grant 1971.001
• CSR Grant 1659.001
• GRC Grant 1598.001
DARPA AMD
ST Microelectronics KeySight
C2S2
• Grant 2047.002.014 Intellasys Corporation


Intel Corporation Soft Machines Soft Machines
Committee on Research, Faculty Research Grant Fudan University
Xilinx Incorporated UC MICRO
Atheros Communications
We also acknowledge support from:
• Artisan
• MOSIS
Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity.

Publications

Publications in review are provided to sponsors but not yet listed here.


2025


• Fnu Sagar Sajeev and Bevan M. Baas,
  "Regular Expression Processing On A Many-Core Platform,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 2025.
  To appear.

• Derek Li, Yechengnuo Zhang, and Bevan M. Baas,
  "Huffman Decoder for Baseline JPEG On Many-Core Platforms,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 2025.
  To appear.

• Michael Wang and Bevan M. Baas,
  "Scalable Discrete Cosine Transform Engines On A Many-Core Platform,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 2025.
  To appear.

• Daniel Chevy and Bevan Baas,
  “Optimizing Internal Data Width in FFT Accelerators for Signal-to-Noise Ratio and Area Efficiency,”
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, October 2025.

• Yechengnuo Zhang, Derek Li, and Bevan Baas,
  “High-Throughput and Small-Area Huffman Decoder for Baseline JPEG Using Small Memory Arrays,”
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, October 2025.

  2024
  

• Michael Wang,
  "Computation of the Discrete Cosine Transform on Many-Core Platforms,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2024.

• Yuxuan Huo,
  "Computing Numerical Functions on Many-Core Processor Arrays,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2024.

  2023
  

• Jin Cui,
  "Dynamic Voltage and Frequency Scaling Controller and Circuits Using Multiple Back Bias Voltages,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2024.

• Santhosh Sammeta,
  "Characterization of a PCIe interface for a Many-Core chip Test Station,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2023.

• Thomas Abbott and Bevan M. Baas,
  "A Scalable JPEG Encoder on a Many-Core Array,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 2023.

• Shifu Wu and Bevan Baas,
  “Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction,”
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, Arizona, August 2023.

• Thomas Abbott,
  "JPEG Encoding on Fine-Grain Manycore Platforms,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, July 2023.

  2022
  

• Satyabrata Sarangi and Bevan M. Baas,
  "Energy-Efficient Canonical Huffman Decoders on Many-Core Processor Arrays and FPGAs,"
  Elsevier, Integration the VLSI Journal,
  In press.

• Peiyao Shi, Aaron Stillmaker, and Bevan M. Baas,
  "Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array,"
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Penang, Malaysia, December 2022.

• Renjie Chen, Aaron Stillmaker, and Bevan M. Baas,
  "Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder,"
  IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022.

• Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, and Bevan M. Baas,
  "A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency,"
  IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022.

• Aidan Callahan,
  "H.264 Codec Implementation on a Many-Core Processor Array,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, November 2022.

• Ziyuan Dong,
  "An Energy-Efficient SqueezeNet Implementation on the KiloCore Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2022.

• Christian Lum,
  "Zero Crossing and Polar Discrimination Algorithms & Hardware for a Digital FM Receiver,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2022.

• Benjamin Moore,
  "An All-Digital FM Reciever Implemented on the Xilinx ZCU111 RFSoC,"
  Masters Thesis Plan II, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2022.

• Tony (Wai Cheong) Tsoi,
  "Post-Silicon Hardware Validation of a Many-Core System,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, May 2022.

  2021
  

• Haotian Wu,
  "Residual Neural Network on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2021.

• Shifu Wu,
  "Design of Display Stream Compression Video Codecs,"
  Ph.D. Dissertation, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2021.

• Yikai Mao,
  "A Memory-Efficient YOLO Object Detection Convolutional Neural Network Inference Engine on the KiloCore 2 Manycore Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2021.

• Shifu Wu and Bevan M. Baas,
  "Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays,"
  IEEE Transactions on Circuits & Systems II, May 2021.
  Invited.

• Satyabrata Sarangi and Bevan M. Baas,
  "DeepScaleTool: a Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era,"
  IEEE International Symposium on Circuits & Systems, Daegu, Korea, May 2021.

• Shifu Wu and Bevan M. Baas,
  "Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays,"
  IEEE International Symposium on Circuits & Systems, Daegu, Korea, May, 2021.
  Received an invitation to an IEEE Transactions on Circuits and Systems II Special Issue.

• Zhangfan Zhao,
  "Matrix Inversion on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2021.

• Sharmila Kulkarni,
  "Implementation of Context-Based Adaptive Binary Arithmetic Coding on KiloCore Processor Arrays,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2021.

• Satyabrata Sarangi and Bevan M. Baas,
  "Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays,"
  IEEE/ACM Asia and South Pacific Design Automation Conference, Tokyo, Japan, January, 2021.
  

  2020
  

• Shifu Wu and Bevan M. Baas,
  "Indexed Color History Many-Core Engines for Display Stream Compression Decoders,"
  IEEE International Conference on Electronics, Circuits & Systems, Glasgow, Scotland, November, 2020.
  

• Tokunbo Ogunfunmi, John McAllister, Bevan Baas and Mrityunjoy Chakraborty,
  "Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop,"
  Journal of Signal Processing Systems, August 2020.

• Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, and Bevan Baas,
  "Scalable Energy-Efficient Parallel Sorting on a Fine-Grained Many-Core Processor Array,"
  Journal of Parallel and Distributed Computing, vol. 138, pp. 32–47, April 2020.

• Daniel Kuzmenko, Carlos Feres, Timothy Andreas, Bevan Baas, Zhi Ding, Xiaoguang Liu, Harris Moyer, Ara Kurdoghlian, Hasan Sharifi,
  "Noncoherent Plug-and-Play RF Front-End Module for High Gain Spread Spectrum Communications and Interference Rejection,"
  Government Microcircuit Applications & Critical Technology Conference (GOMACTech), San Diego, CA, March 2020.

• Arthur Hlaing,
  "Long Short-Term Memory on a Many-Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2020.

• Brent Bohnenstiehl,
  "Design and Programming of the KiloCore Processor Arrays,"
  Ph.D. Dissertation, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2020.

  2019
  

• Renjie Chen,
  "Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

• Christi Tain,
  "Back-end Physical Design Flow for 28 nm FDSOI with Body-Bias,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

• Filipe Borges,
  "AlexNet Deep Neural Network on a Many Core Platform,"
  Masters Thesis, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2019.

  2018
  

• Peiyao Shi,
  "Sparse Matrix Multiplication on a Many-Core Platform,"
  Masters Thesis, Technical Report ECE-VCL-2018-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2018.

• Shifu Wu, Snehlata Gutgutia, Massimo Alioto and Bevan Baas,
  “Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,”
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, October 2018.

• Bevan Baas, Brent Bohnenstiehl, and Jin Cui,
  “Exploration of Fine-Grain Body Bias Control in Many-Core Processor Arrays,”
  IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, October 2018.
  Invited.

• Shifu Wu and Bevan Baas,
  “A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding,”
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, August 2018.

  2017
  

• Jon Pimentel,
  "Methods for Reducing Floating-Point Computation Overhead,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2017-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2017.

• Michael Braly, Aaron Stillmaker and Bevan Baas,
  "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture for Realtime 4K Video Encoding in 65nm CMOS,"
  In Proceedings of the IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, August 2017.

• Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
  "The Design of the KiloCore Chip,"
  ACM/IEEE Design Automation Conference, (DAC), Austin, TX, June 2017.
  Invited.

• Aaron Stillmaker and Bevan Baas,
  "Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm,"
  Integration, the VLSI Journal, vol. 58, pp. 74–81, June 2017.
  

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A 32 nm 1000-Processor Computational Array,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 4, pp. 891–902, April 2017.
  Invited.

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A Fine-Grained 1000 Processor Array for Task Parallel Applications,"
  IEEE Micro, vol.37, no.2, pp. 63-69, March-April 2017.
  Invited.

• Emmanuel O. Adeagbo,
  "Energy-Efficient Pattern Matching Methods on a Fine-Grained Many-Core Platform,"
  Masters Thesis, Technical Report ECE-VCL-2017-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2017.

  2016
  

• Bin Liu,
  "Energy-Efficient Computing with Fine-grained Many-Core Systems,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2016-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2016.

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "KiloCore: A 32 nm 1000-Processor Array,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips (HotChips 2016), Cupertino, CA, August 2016.
  Received an invitation to an IEEE Micro Special Issue.

• Jon Pimentel, Brent Bohnenstiehl and Bevan Baas,
  "Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 25, no. 1, pp. 100-113, January 2017. (Official date of publication July 12, 2016).

• Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
  "A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32 nm 1000-Processor Array,"
  Symposium on VLSI Circuits, Honolulu, HI, June 2016.
  Received an invitation to an IEEE Journal of Solid-State Circuits (JSSC) Special Issue.

  2015
  

• Aaron Stillmaker,
  "Design of Energy-Efficient Many-Core MIMD GALS Processor Arrays in the 1000-Processor Era,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2015-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2015.

• Michael Braly,
  "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture Suitable for Realtime 4K Video Encoding,"
  Masters Thesis, Technical Report ECE-VCL-2015-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2015.

• Jon Pimentel, Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
  "Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2015.
  

• Brent Bohnenstiehl and Bevan Baas,
  "A Software LDPC Decoder Implemented on a Many-Core Array of Programmable Processors,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2015.
  

• Emmanuel O. Adeagbo and Bevan Baas,
  "Energy-Efficient String Search Architectures on a Fine-Grained Many-Core Platform,"
  Technology and Talent for the 21st Century (TECHCON 2015), Austin, TX, September 2015.

• Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi and Bevan Baas,
  "Optimizing Power of Many-Core Systems by Exploiting Dynamic Voltage, Frequency and Core Scaling,"
  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, August 2015.
  Best Student Paper Award, Third Place.

  2014
  

• Jon Pimentel and Bevan Baas,
  "Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2014.
  Best Student Paper Award, Third Place.

• Bin Liu, Brent Bohnenstiehl and Bevan Baas,
  "Scalable Hardware-Based Power Management for Many-Core Systems,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2014.
  

• Jon Pimentel and Bevan Baas,
  "Software/Hardware Hybrid Floating-Point Units with Low Area Overhead on a Fine-Grained Processing Core,"
  Technology and Talent for the 21st Century (TECHCON 2014), Austin, TX, September 2014.

• Nima Mostafavi,
  "Hardware, Software, and Tools for an AsAP2 Many-Core System,"
  Masters Thesis, Technical Report ECE-VCL-2014-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2014.

• Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan Baas and Soheil Ghiasi,
  "Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms,"
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 5, pp. 752-762, May 2014.

  2013
  

• Zhibin Xiao and Bevan Baas,
  "A Hexagonal Processor and Interconnect Topology for Many-core Architecture with Dense On-Chip Networks,"
  Book Chapter in IFIP Advances in Information and Communication Technology, Springer, 2013.
  Invited.

• Aaron Stillmaker, Lucas Stillmaker, Brent Bohnenstiehl and Bevan M. Baas,
  "Energy-Efficient Sorting on a Many-Core Platform,"
  Technology and Talent for the 21st Century (TECHCON 2013), Austin, TX, September 2013.

• Anh Tran and Bevan Baas,
  "Achieving High-Performance On-Chip Networks with Shared-Buffer Routers,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1391-1403, June 2014. (Official date of publication July 3, 2013.)

• Zhibin Xiao and Bevan Baas,
  "Processor Tile Shapes and Interconnect Topology for Dense On-Chip Networks,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 6, pp. 1377-1390, June 2014. (Official date of publication June 25, 2013.)

• Bin Liu and Bevan Baas,
  "Parallel AES Encryption Engines for Many-Core Processor Arrays,"
  IEEE Transactions on Computers, vol. 62, no. 3, pp. 536-547, March 2013.
  

• Rasit Topaloglu and Bevan Baas,
  "Guest Editors' Introduction to Practical Parallel EDA,"
  IEEE Design & Test, vol. 30, Issue 1, February 2013.
  

• Tinoosh Mohsenin, Houshmand Shirani-Mehr and Bevan Baas,
  "LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization,"
  VLSI Design, vol. 2013, 14 pages, February 2013.
  

  2012
  

• Zhibin Xiao,
  "Energy-efficient Fine-grained Many-core Architecture for Video and DSP Applications,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2012-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2012.

• Aaron Stillmaker, Lucas Stillmaker and Bevan M. Baas,
  "Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array."
  IEEE International Conference on Parallel and Distributed Systems (ICPADS 2012), Singapore, December 2012

• Zhibin Xiao and Bevan Baas,
  "A Hexagonal Shaped Processor and Interconnect Topology for Tightly-tiled Many-core Architecture,"
  IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Santa Cruz, CA, Oct. 2012.
  Received an invitation to a Book Chapter.

• Anh Tran,
  "On-Chip Network Designs for Many-Core Computational Platforms,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2012-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, August 2012.
  UC Davis College of Engineering 2013 Zuhair A. Munir Award for Best Doctoral Dissertation, Honorable Mention

• Anh Tran and Bevan Baas,
  "NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip,"
  Technical Report ECE-VCL-2012-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, July 2012.

• Houshmand Shirani-Mehr,
  "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders,"
  Masters Thesis, Technical Report ECE-VCL-2012-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, June 2012.

• Bin Liu and Bevan Baas,
  "Energy-Efficient AES Ciphers on a Fine-Grained Many-Core System ,"
  Technology and Talent for the 21st Century (TECHCON 2012), Austin, TX, Sep. 2012
  

• Allen Baum and Bevan Baas,
  "Introduction to the Special Issue: Hot Chips 23,"
  IEEE Micro, Volume 32, Number 2, March/April 2012.

• Zhibin Xiao and Bevan Baas,
  "Processor Shapes and Topologies for Dense On-chip Networks,"
  presented in the IEEE International Solid-Sate Circuit Conference (ISSCC 2012) student forum, San Francisco, CA, Feb. 2012.
  

  2011
  

• Aaron Stillmaker, Zhibin Xiao and Bevan Baas,
  "Toward More Accurate Scaling Estimates of CMOS Circuits from 180 nm to 22 nm,"
  Technical Report ECE-VCL-2011-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2011.

• Trevin Murakami,
  "A SystemC Single-Cycle Simulator,"
  Masters Thesis, Technical Report ECE-VCL-2011-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2011.

• Bin Liu and Bevan Baas,
  "A High-Performance Area-Efficient AES Cipher on a Many-Core Platform,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2011.
  Nominated for Best Student Paper.

• Houshmand Shirani-Mehr, Tinoosh Mohsenin and Bevan Baas,
  "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2011.
  

• Zhibin Xiao, Stephen Le and Bevan Baas,
  "A Fine-Grained Parallel Implementation of a H.264/AVC Encoder on a 167-processor Computational Platform,"
  IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 2011.
  

• Anh Tran and Bevan Baas,
  "RoShaQ: High-Performance On-Chip Router with Shared Queues,"
  IEEE International Conference on Computer Design (ICCD), Amherst, MA, October 2011, pp. 232-238.
  Best Paper Award.

• Lucas Stillmaker,
  "SAISort: An Energy Efficient Sorting Algorithm for Many-Core Systems,"
  Masters Thesis, Technical Report ECE-VCL-2011-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2011.

• Anh Tran and Bevan Baas,
  "Design of Bufferless On-Chip Routers Providing In-Order Packet Delivery,"
  SRC Technology and Talent for the 21st Century (TECHCON), Austin, TX, USA, Sep. 2011, S14.3.

• Emmanuel Adeagbo, and Stephen Lewis,
  "A Band-Gap Reference with Internal Digital Signal Processing,"
  Technical Report ECE-2011, VLSI Computation Laboratory, Solid State Circuits Research Laboratory, ECE Department, University of California, Davis, July 2011.

• Zhibin Xiao and Bevan Baas,
  "A 1080p H.264/AVC Baseline Residual Encoder for a Fine-grained Many-core System,"
  IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 7, pp. 890-902, July 2011.
  

• Bevan M. Baas,
  "A case for fine-grained many-core processor arrays,"
  Parallel Algorithms, Programming, Architectures Workshop at the 48th ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 5, 2011.
  Invited.

• Tinoosh Mohsenin, Houshmand Shirani-Mehr and Bevan Baas,
  "Low Power LDPC Decoder with Efficient Stopping Scheme for Undecodable Blocks,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 2011.
  Invited*.

• Jeremy W. Webb,
  "A High Performance Baseband Instrument,"
  Masters Thesis, Technical Report ECE-VCL-2011-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2011.

  2010
  

• Tinoosh Mohsenin,
  "Algorithms and Architectures for Efficient Low Density Parity Check (LDPC) Decoder Hardware,"
  Ph.D. Dissertation, Technical Report ECE-VCL-2010-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, November 2010.

• Emmanuel Adeagbo, and Stephen O'Driscoll,
  "Implantable Radio Transmitters for Long Range Health Monitoring,"
  Technical Report ECE-2011, VLSI Computation Laboratory, Solid State Circuits Research Laboratory, ECE Department, University of California, Davis, December 2010.

• Dean Truong and Bevan Baas,
  "Massively Parallel Processor Array for Mid-/Back-end Ultrasound Signal Processing,"
  In Proceedings of the IEEE Biomedical Circuits and Systems Conference (BioCAS), Paphos, Cyprus, Nov. 2010, pp. 274-277.
  Nominated for Best Student Paper.

• Anh Tran and Bevan Baas,
  "DLABS: a Dual-Lane Buffer-Sharing Router Architecture for Networks on Chip,"
  In Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS), Cupertino, CA, Oct. 2010, pp. 331-336.
  

• Zhibin Xiao, Stephen Le and Bevan Baas,
  "An Energy-Efficient Parallel H.264/AVC Baseline Encoder on a Fine-grained Many-core System,"
  Technology and Talent for the 21st Century (TECHCON 2010), Austin, TX, Sep. 2010.
  

• Anh Tran and Bevan Baas
  "Design of an Energy-Efficient 32-bit Adder Operating at Subthreshold Voltages in 45-nm CMOS",
  International Conference on Communications and Electronics (ICCE), Aug. 2010, pp. 87-91.
  

• Anh Tran, Dean Truong and Bevan Baas,
  "A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms,"
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 6, pp. 897-910, June 2010.
  Invited.

• Dean Truong and Bevan Baas,
  "Circuit Modeling for Practical Many-core Architecture Design Exploration,"
  In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 627-628.
  Wild And Crazy Ideas (WACI) Session.
  "WACIest" Best-In-Session Paper.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "A Low-Complexity Message Passing Algorithm for Reduced Routing Congestion in LDPC Decoders,"
  IEEE Transactions of Circuits and Systems I (TCAS-I), vol. 57, no. 5, pp. 1048-1061, May 2010.
  Invited. (32 invited papers submitted, 13 accepted)

• Zhiyi Yu and Bevan Baas,
  "A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 18, no. 5, pp. 750-762, May 2010.

• Stephen Le,
  "A Fine Grained Many-Core H.264 Video Encoder,"
  Masters Thesis, Technical Report ECE-VCL-2010-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, March, 2010.

• Tinoosh Mohsenin and Bevan Baas,
  "A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders,"
  Journal of Signal Processing Systems for Signal, Image, and Video Technology, available online, Feb. 2010.

  2009
  

• Gouri Landge,
  "A Configurable Motion Estimation Accelerator For Video Compression,"
  Masters Thesis, Technical Report ECE-VCL-2009-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December, 2009.

• Tinoosh Mohsenin and Bevan Baas,
  "Trends and Challenges in LDPC Hardware Decoders,"
  IEEE Asilomar Conference on Signals, Systems and Computers, November 2009, pp. 1273-1277.
  Invited.

• Tinoosh Mohsenin and Bevan Baas,
  "High Throughput and Energy Efficient LDPC Decoders using Multi-Split-Row Threshold Method,"
  TECHCON 2009, Sept. 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "An Improved Split-Row Thresholding Decoding Algorithm for LDPC Codes,"
  In Proceedings of the IEEE International Conference on Communications (ICC'09), June 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "Multi-Split-Row Threshold Decoding Implementations for LDPC Codes,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009, pp. 2449-2452.
  Received an invitation to an IEEE Transactions on Circuits and Systems I (TCAS-I) Special Issue. (only 40 invited out of 817?)

• Anh Tran, Dean Truong and Bevan Baas,
  "A Low Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009, pp. 996-999.

• Anthony Jacobson, Dean Truong and Bevan Baas,
  "The Design of a Reconfigurable Continuous-Flow Mixed-Radix FFT Processor,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009, pp. 1133-1136.

• Anh Tran, Dean Truong and Bevan Baas,
  "A GALS Many-Core Heterogeneous DSP Platform with Source-Synchronous On-Chip Interconnection Network,"
  In Proceedings of the ACM/IEEE International Symposium on Networks on Chip (NOCS) , May 2009, pp. 214-223.
  Received an invitation to an IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Special Issue.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy Webb, Paul Mejia, Bevan Baas,
  "A 167-Processor Computational Platform in 65 nm CMOS,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 4, pp. 1130-1144, April 2009.
  Invited.

• Zhiyi Yu and Bevan Baas,
  "High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 17, no. 1, pp. 66-79, Jan. 2009.

  2008
  

• Zhiyi Yu and Bevan Baas,
  High Performance and Energy Efficient Many-Core DSP Systems,
  VDM Publishing House Ltd., December 2008. Available at amazon.com.
  Invited.

• S. J. Yoo, V. Akella, R. Amirtharajah, B. Baas, K. Bergman, S. Fan, J. Harris, D. Miller, M. Lipson, J. Shalf.
  "Balanced Computing with Nanophotonic Interconnects."
  The 21st Annual Meeting of the IEEE Lasers & Electro-Optics Society, November 2008, pp. 368-369.
  Invited.

• Tinoosh Mohsenin, Pascal Urard and Bevan Baas,
  "A Thresholding Algorithm for Improved Split-Row Decoding of LDPC Codes,"
  IEEE Asilomar Conference on Signals, Systems and Computers, October 2008, MA8b1-8.

• Anh Tran, Dean Truong and Bevan Baas,
  "A Complete Real-Time 802.11a Baseband Receiver Implemented on an Array of Programmable Processors,"
  IEEE Asilomar Conference on Signals, Systems and Computers, October 2008, pp. 165-170.

• Zhibin Xiao and Bevan Baas,
  "A High-Performance Parallel CAVLC Encoder on a Fine-Grained Many-core System,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2008, pp. 248-254.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2008), August 2008.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling,"
  In Proceedings of the Symposium on VLSI Circuits, June 2008, C3.1., pp. 22-23.
  Received an invitation to an IEEE Journal of Solid-State Circuits (JSSC) Special Issue.

• Zhiyi Yu and Bevan Baas,
  "A Low-Area Interconnect Architecture for Chip Multiprocessors,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 2008, pp. 2857-2860.

• Wayne Cheng and Bevan Baas,
  "Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 2008, pp. 1236-1239.

• V. Akella, R. Amirtharajah, B. Baas, K. Bergman, V. Carey, S. Fan, J. Harris, S. Islam, M. Lipson, K. Liu, D. Miller, J. Shalf, S. J. Yoo.
  "Energy-Efficient and Balanced Computing with Nanophotonic Interconnects and their Temperature-Insensitive Operation,"
  HP Labs Photonic Interconnect Forum, 2008.

• Tinoosh Mohsenin and Bevan Baas,
  "An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder,"
  IEEE International Solid-State Circuits Conference (ISSCC) 2008 Student Forum, February 2008.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas,
  "Architecture and Evaluation of an Asynchronous Array of Simple Processors,"
  Journal of Signal Processing Systems, March 2008.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
  "AsAP: An Asynchronous Array of Simple Processors,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

• Wayne H. Cheng,
  "Approaches and Designs of Dynamic Voltage and Frequency Scaling,"
  Masters Thesis, Technical Report ECE-CE-2008-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2008.

  2007
  

• Zhiyi Yu,
  "High Performance and Energy Efficient Multi-core Systems for DSP Applications,"
  Ph.D. Dissertation, Technical Report ECE-CE-2007-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.
  Received an invitation to publish the dissertation as a book.

• Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas,
  "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

• Eric W. Work,
  "Algorithms and Software Tools for Mapping Arbitrarily Connected Tasks onto an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2007-4, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Anthony T. Jacobson,
  "A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT Processor,"
  Masters Thesis, Technical Report ECE-CE-2007-3, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung,
  "AsAP: A Fine-Grained Many-Core Platform for DSP Applications,"
  IEEE Micro, Volume 27, Number 2, March/April 2007.
  Invited.

• Michael Meeuwsen, Zhiyi Yu, and Bevan Baas,
  "A Shared Memory Module for Asynchronous Arrays of Processors,"
  EURASIP Journal on Embedded Systems, vol. 2007, Article ID 86273, 13 pages, 2007.

• Tinoosh Mohsenin and Bevan M. Baas,
  "High-Throughput LDPC Decoders Using A Multiple Split-Row Method,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '07), April 2007.

  2006
  

• Zhiyi Yu and Bevan M. Baas,
  "Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles ,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD '06), October 2006, pp. 174-179.

• Tinoosh Mohsenin and Bevan M. Baas,
  "Split-row: A reduced complexity, high throughput LDPC decoder architecture ,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD '06), October 2006, pp. 320-325.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin,
  "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2006), August 2006.
  Received an invitation to an IEEE Micro Special Issue.

• Zhiyi Yu and Bevan M. Baas,
  "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems,"
  In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '06), March 2006, pp. 378-384.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas,
  "An Asynchronous Array of Simple Processors for DSP Applications,"
  In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, pp. 428-429, 663.

  2005 and prior
  

• Michael J. Meeuwsen,
  "A Shared Memory Module for an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2005-2, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2005.

• Bevan M. Baas,
  "A Generalized Cached-FFT Algorithm,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2005, March 2005, pp. V-89-92.

• Michael J. Meeuwsen, Omar Sattari, and Bevan M. Baas,
  "A Full-Rate Software Implementation of an IEEE 802.11a Compliant Digital Baseband Transmitter,"
  In Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '04), Oct. 2004.

• Ryan W. Apperson,
  "A Dual-Clock FIFO for the Reliable Transfer of High-Throughput Data Between Unrelated Clock Domains,"
  Masters Thesis, Technical Report ECE-CE-2004-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Michael A. Lai,
  "Arithmetic Units for a High Performance Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-6, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Omar Sattari,
  "Fast Fourier Transforms on a Distributed Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-7, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Bevan M. Baas,
  "A Parallel Programmable Energy-Efficient Architecture For Computationally-Intensive DSP Systems,"
  IEEE Asilomar Conference on Signals, Systems and Computers, 37th, November 2003.

• Howard CheHao Chang and Bevan M. Baas,
  "Mapping an FIR Filter to a 2-Dimensional Mesh of Processors,"
  Technical Report ECE-CE-2003-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2003.

• J. Thomson, B. Baas, et al.,
  "An Integrated 802.11a Baseband and MAC Processor,"
  International Solid-State Circuits Conference (ISSCC), February 2002.

• Bevan M. Baas,
  "A Low-Power, High-Performance, 1024-point FFT Processor,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 34, no. 3, pp. 380-387, March 1999.
  Invited.

• Bevan M. Baas,
  "An Approach to Low-Power, High-Performance, Fast Fourier Transform Processor Design,"
  Ph.D. Dissertation, Department of Electrical Engineering, Stanford University, February 1999.

• Bevan M. Baas,
  "A 9.5 mW 330 μsec 1024-point FFT Processor,"
  IEEE Custom Integrated Circuits Conference (CICC), May 1998.

• G. L. Tyler, B. M. Baas, F. Bauregger, S. Mitelman, I. Linscott, E. Post, O. Shana'a, and J. Twicken,
  "Radioscience Receiver Development for Low Power, Low Mass Up-Link Missions,"
  Planetary Instrumentation Definition and Development Program Workshop, Jet Propulsion Laboratory, June 1997.

• James B. Burr, Zongjian Chen, and Bevan M. Baas,
  "Stanford Ultra-Low-Power CMOS Technology and Applications,"
  In Low-Power HF Microelectronics, a Unified Approach, Chapter 3, pp. 85-138. The Institution of Electrical Engineers, London, UK, June 1996.

• Bevan M. Baas,
  "An Energy-Efficient Single-Chip FFT Processor,"
  Symposium on VLSI Circuits, June 1996.
  Received an invitation to an IEEE Journal of Solid-State Circuits (JSSC) Special Issue.

• Bevan M. Baas,
  "An Energy-Efficient FFT Processor Architecture,"
  Technical Report NST-70340-1994-1, STARLab, EE Department, Stanford University, January 1994.

• Bevan M. Baas,
  "A Pipelined Memory System For an Interleaved Processor,"
  Technical Report NSF-GF-1992-1, STARLab, EE Department, Stanford University, June 1992.

• KiloCore 1000-processor chip
  • Reported in publications such as: Ars Technica, Daily Mail, Digital Journal, EE Times, Electronics Weekly, Engadget, Enterprise Tech, ExtremeTech, Financial Express, Gadget Mash, Inquirer, Mashable, Motherboard, NDTV, Next Big Future, NSF Science 360 Video News, PC Magazine, PC Review, PC World, The Register, Science Daily, SlashGear, Tech Switch, Tech Times, The Next Platform, The Verge, Wired, ZDNet, and more than 100 others...

• New 167-processor chip is super-fast, ultra energy-efficient
  • EurekAlert news service operated by AAAS TechRadar, UC Davis News Service, and many others.

• New scalable algorithms, layouts, and mappings for Scientific kernels such as matrix multiplication, sparse matrix operations, inversion, and others

• New scalable algorithms, layouts, and mappings for Machine learning applications

• Processor simulation, emulation, and CAD design flow

• Code scheduler programming tool (update to new architecture and new capabilities)

• General domain: Programmable DSP processor design

• General domain: Parallel DSP algorithms

• General domain: Reconfigurable inter-processor networks for various network traffic styles

• General domain: Functional unit and circuit design

• Development of our C compiler for our many-core processor arrays

• Arbitrary graph mapping algorithms and tools

• Dynamic supply voltage and clock frequency circuits and algorithms

• Shorter-term projects (for undergraduate, MS, or Ph.D. starter projects)
  • Measurement and characterization of our multi-core chips (longer term)
  • System-level applications utilizing our AsAP2 + workstation + FPGA platform
  • I/O delay auto-calibration for our AsAP2 + workstation + FPGA platform
  • Second generation FFT accelerator processor
  • FPGA implementations of Wi-Fi, H.264, FFT, AES, and other applications
    Compare fpgas/many-core commercial/own-design: programming tools, layout area, energy for functions
  • Full H.264 encoder and decoder on AsAP array
  • Various FFTs on AsAP array
  • Chip design CAD tool projects
  • Arbitrary graph drawing program
  • Quick: bibtex processing script (authors)
  • Quick: dircmp (script to recursively diff directories of files)

• A note to interested prospective students

• NoCTweak: a Highly Parameterizable Networks-On-Chip Simulator
  
  
• Arbitrary Graph to 2D Mesh Mapping Tool
  
  
• Low overhead parallel-task linux based simulator
  
  
• Dual-clock FIFO
  
  

• Directions to the VCL lab

• Some VCL Guidelines for students in the VCL lab (good computer etiquette, writing papers, responding to reviewers)

• Unix command notes, Unix tutorials, LaTeX notes

• Information on the FPGA boards used in the lab

• Getting started in the VCL lab

Laboratory Resources

In addition to significant computing resources, the VCL owns a large number of electronic test and measurement instruments. These include the following Agilent and Tektronix instruments:
• TLA7012 Logic Analyzer with
  • 7PG2 64-channel pattern generator module 1M/channel memory and
  • 7AA2 68-channel logic analyzer 512K/channel memory,
• TDS7154B 4-channel 20 GSample/sec 1.5 GHz 4M/channel memory oscilloscope,
• 54831D 4+16-channel 4 GSample/sec 600 MHz oscilloscope,
• TDS5034B 4-channel 350 MHz oscilloscope,
• 81130A 660 MHz pulse generator,
• AFG3252 2 GSample/sec 120 MHz Arbitrary Waveform Generator,
• (5) 6611C, 6611C, and 6631B Precision Power Supplies,
• (11) E3642A, E3644A, E3633A, E3610A power supplies, and
• a wide variety of multimeters, probes and other equipment and supplies.
Virtually all instruments are GPIB (IEEE 488)-controllable and are connected to the laboratory's instrumentation control network. In addition to the group's instruments, through a sharing agreement with other groups in the Kemper 2201 laboratory, we have access to a vast array of other test and measurement equipment.

General Informative Web Pages

• Many-Core Fabricated Chips Information Page

• Fabricated Programmable Processors Designed in Academia Information Page

• Fabricated SIMD Processors Information Page

• General Purpose Desktop GPU Information Page

• VLSI & Sig. Processing conferences, Our favorite conferences,
  Our favorite conferences II
  Digital VLSI Conferences, Chalmers

Some of the CAD and Other Tools We Use

• Some tools installed locally
• Cadence
  • Tool notes
  • NC verilog
  • SoC Encounter
  • Virtuoso
• Synopsys
  • Design Compiler
  • HSpice
  • NanoSim
• Mentor Graphics
  • Calibre
  • Expedition
• Magic layout tool
  • Magic web site
• LaTeX
  • Notes for LaTeX on Windows, v1.0
• Tutorial web pages
  • Cadence, NCSU, and various tutorials

Other Useful Links

• IEEE papers
  • JSSC
  • TVLSI
  • TCAS I: Regular papers;
  Publication statistics
  • TCAS II: Express briefs
• Intl. Tech. Roadmap for Semiconductors (ITRS)
• MOSIS web site
• Future technology spice decks from UCB's Predictive Technology Model
• Accurel for FIBing, packaging,...
• AsAP Wikipedia page
• gds2pov, a 3D GDSII visualization tool

Informative References

• LaTeX: Formulas,
• Deep chip's CAD tool review from CAD '04

Last update: October 30, 2019
Keywords: many-core, multi-core, array processor, homogenous, heterogeneous, NoC, network on chip, interconnect, mesh, GALS, globally asynchronous locally synchronous, electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, ASIC, FPGA, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver, H.264 video compresssion encoding decoding, encoder decoder, codec, AES encryption decryption, networks on-chip, on-chip networks, routers, source-synchronous, interconnects, interconnection