Goal is to cut verification time by 25%.
created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow.
This is a big deal in verification because it allows horizontal reuse of a . Test patterns run on the processors in a design and that enables the test to be run on a , simulator, emulator, FPGA prototype or even the fabricated chip. This also paves the way to a mechanism for defining end-user scenarios for the product. Because SoCs contain many processors these days, leaving them in the design while being tested makes more sense, rather than having to take them out, which is what’s done now using the Universal Verification Methodology (). In effect, this is testing from the inside out rather than outside in.
Faris Khundakjie, the group’s chair, and a senior verification engineer at Intel, estimated that a standardized way of writing portable test and stimulus could shave 25% off the overall verification time, which is significant given that an estimated 50% to 80% of NRE is on the verification side. He said there is strong interest and a sense of urgency from around the industry in getting a standard in place, with a prototype possible within a year, the first version rolling out in two years, and technology backing this up trickling into R&D after that.
“There are multiple efficiency points to be gained and leaps in verification productivity,” said Khunkakjie, citing everything from pre-silicon to emulation, FPGA prototyping all the way to post-silicon validation. “Today there are camps of engineers with little communication between them. The goal is to have re-use of at least a subset of stimuli, so you can write it once and re-use it across multiple platforms. That way different camps of engineers can work from a coherent spec.”
In April 2014 there was an exploratory meeting to discuss the formation of this working group. Accellera said at the time: “It was agreed by the board that a broader scope beyond graph-based testbench would be more beneficial. The name of the group is ‘Portable Stimulus Proposed Working Group.’ The group is in the early stages of development. The next step is to send out a call for participation. The Proposed Working Group will look at all proposals, level of interest, and then decide if it’s practical to pursue this activity in a new working group.”
That working group has now been formed. Accellera said 37 people from 20 companies participated in the group, representing semiconductor suppliers, systems houses, EDA vendors, and IP providers. The group will have its kickoff meeting on March 5 to establish a mission statement, goals, milestones and roadmap, while developing a Design Objective Document.
For more information about the group and to learn how to join and participate, click here.
—Ed Sperling contributed to this report.
