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Re: [Xen-users] Re: [Xen-devel] VMX Hardware

To: Anthony Liguori <aliguori@xxxxxxxxxx>
Subject: Re: [Xen-users] Re: [Xen-devel] VMX Hardware
From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
Date: 2005年8月14日 19:23:14 +0100
Cc: Goetz Bock <bock@xxxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxx, xen-users@xxxxxxxxxxxxxxxxxxx, monz@xxxxxxxxx
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On 14 Aug 2005, at 19:09, Anthony Liguori wrote:
The Pacifica spec does mention optional hardware support for "Nested Page Tables" which is essentially hardware shadow page tables. Should be interesting to see the performance difference between software/hardware shadow page tables.
I have doubts about the performance of hardware page tables, unless there's a clever TLB design. A pagetable walk which is four memory accesses on normal x86/64 becomes twenty accesses in nested mode! It may be that shadow pagetables, by providing a bigger 'cache' for guest->host mappings, can actually perform better on many workloads. I guess we'll see -- if silicon is produced that supports that mode, someone is bound to add support to Xen.
 -- Keir
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