| To: | <xen-devel@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | [Xen-devel] [PATCH] Mask AMD CPUID masks in software before writing them to the MSRs. |
| From: | Tim Deegan <Tim.Deegan@xxxxxxxxxx> |
| Date: | 2010年2月16日 17:21:48 +0000 |
| Delivery-date: | 2010年2月16日 09:22:36 -0800 |
| Envelope-to: | www-data@xxxxxxxxxxxxxxxxxxx |
| List-help: | <mailto:xen-devel-request@lists.xensource.com?subject=help> |
| List-id: | Xen developer discussion <xen-devel.lists.xensource.com> |
| List-post: | <mailto:xen-devel@lists.xensource.com> |
| List-subscribe: | <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe> |
| List-unsubscribe: | <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe> |
| Sender: | xen-devel-bounces@xxxxxxxxxxxxxxxxxxx |
| User-agent: | Mutt/1.5.18 (2008年05月17日) |
Mask AMD CPUID masks in software before writing them to the MSRs. Setting bits in the CPUID mask MSR that are not set in the unmasked CPUID response can cause those bits to be set in the masked response. Avoid that by explicitly masking in software. Signed-off-by: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Attachment:
amd-cpuidmask
Description: Text document
_______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | [Xen-devel] RE: Tmem vs order>0 allocation, workaround RFC , Dan Magenheimer |
|---|---|
| Next by Date: | [Xen-devel] AMD extended migration CPU masks: why only on CPU 0? , Tim Deegan |
| Previous by Thread: | Re: [Xen-devel] Kernel 2.6.31.6 pv_ops freeze on start , Fantu |
| Next by Thread: | [Xen-devel] AMD extended migration CPU masks: why only on CPU 0? , Tim Deegan |
| Indexes: | [Date] [Thread] [Top] [All Lists] |