This patch corrects emulation errors in QEMU's 16550 uart emulation,
which cause compatibility issues with FreeBSD's uart(9) driver.
 o Implement receive overrun status. The FreeBSD uart(9) driver
 relies on this status in it's probe routine to determine the size
 of the FIFO supported.
 o As per the 16550 spec, do not overwrite the RX FIFO on an RX overrun.
 o Do not allow TX or RX FIFO overruns to increment the data valid count
 beyond the size of the FIFO.
 o For reads of the IIR register, only clear the "TX holding register
 empty" (THRE) interrupt if the read reports this interrupt. This
 is required by the specification and avoids losing TX interrupts
 when other, higher priority interrupts (usually RX) are reported first.
This patch also includes a fix for a second cause of lost TX interrupts,
which was submitted by Jergen Lock, and is already in the latest QEMU.
 o If a receive interrupt is suppressed due to the FIFO not yet filling
 to its interrupt threshold, do not also supress any pending THRE
 interrupt.
A version of this patch, against the latest QEMU, has also been submitted
to the qemu-devel mailing list.
Signed-off-by: Justin T. Gibbs <gibbs@xxxxxxxxxxx>
Index: xen-4.0.0-testing/tools/ioemu-remote/hw/serial.c
===================================================================
--- xen-4.0.0-testing.orig/tools/ioemu-remote/hw/serial.c
+++ xen-4.0.0-testing/tools/ioemu-remote/hw/serial.c
@@ -159,11 +159,19 @@
 {
 SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
- f->data[f->head++] = chr;
+ /* Receive overruns do not overwrite FIFO contents. */
+ if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
- if (f->head == UART_FIFO_LENGTH)
- f->head = 0;
- f->count++;
+ f->data[f->head++] = chr;
+
+ if (f->head == UART_FIFO_LENGTH)
+ f->head = 0;
+ }
+
+ if (f->count < UART_FIFO_LENGTH)
+ f->count++;
+ else if (fifo == RECV_FIFO)
+ s->lsr |= UART_LSR_OE;
 return 1;
 }
@@ -195,12 +203,10 @@
 * this is not in the specification but is observed on existing
 * hardware. */
 tmp_iir = UART_IIR_CTI;
- } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) {
- if (!(s->fcr & UART_FCR_FE)) {
- tmp_iir = UART_IIR_RDI;
- } else if (s->recv_fifo.count >= s->recv_fifo.itl) {
- tmp_iir = UART_IIR_RDI;
- }
+ } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
+ (!(s->fcr & UART_FCR_FE) ||
+ s->recv_fifo.count >= s->recv_fifo.itl)) {
+ tmp_iir = UART_IIR_RDI;
 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 tmp_iir = UART_IIR_THRI;
 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
@@ -523,8 +529,10 @@
 break;
 case 2:
 ret = s->iir;
- s->thr_ipending = 0;
- serial_update_irq(s);
+ if (ret & UART_IIR_THRI) {
+ s->thr_ipending = 0;
+ serial_update_irq(s);
+ }
 break;
 case 3:
 ret = s->lcr;
@@ -534,9 +542,9 @@
 break;
 case 5:
 ret = s->lsr;
- /* Clear break interrupt */
- if (s->lsr & UART_LSR_BI) {
- s->lsr &= ~UART_LSR_BI;
+ /* Clear break and overrun interrupts */
+ if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
+ s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 serial_update_irq(s);
 }
 break;
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