I'm not sure if the number of the saved cycles is the same on recent Intel 
CPUs, so the proportion may not be greater. :-)
Thanks,
-- Dexuan
-----Original Message-----
From: Keir Fraser [mailto:keir.fraser@xxxxxxxxxxxxx] 
Sent: 2009?9?16? 16:21
To: Cui, Dexuan; Kouya Shimura
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: Re: [Xen-devel] [PATCH] x86 hvm: freeze PIT/LAPIC timer emulation 
while its IRQ is masked
On 16/09/2009 09:00, "Cui, Dexuan" <dexuan.cui@xxxxxxxxx> wrote:
> Looks the little win doesn't deserve the increased complexity in code.
>
> BTW, recent Intel CPUs run much faster with respect to VMEntry/VMExit and
> VMREAD/VMWRITE, so I don't think the SW optimizatin is appearling here. :-)
Makes it more appealing doesn't it? As this path will be a greater
proportion of an overall vmexit/vmenter cycle.
 -- Keir
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