I'm just wondering if this is really needed. See my response to Wei Wang.
Thanks
--jyh
Keir Fraser wrote:
> Are you questioning whether this patch should be applied?
>
> -- Keir
>
> On 20/07/2009 15:26, "Jiang, Yunhong" <yunhong.jiang@xxxxxxxxx> wrote:
>
>> I assume guest should disable the MMIO in PCI_COMMAND before writing
>> all "1"s to bar register. Otherwise, what will happen on native if
>> guest try to access 0xFFFFFFF0? And if we do update the P2M, will it
>> cause trouble to Xen HV? 
>> 
>> Thanks
>> Yunhong Jiang
>> 
>> xen-devel-bounces@xxxxxxxxxxxxxxxxxxx wrote:
>>> Hi,
>>> When guest code tries to get the block size of mmio, it will write
>>> all "1"s into pci bar register and then qemu will return all "0"s
>>> to the don't care bits in the emulated bar register to indicate the
>>> block size 
>>> to guest code.
>>> In this case, we should not create p2m mapping in
>>> pt_bar_reg_write() and
>>> pt_exp_rom_bar_reg_write(). Attached patch fixes this issue,
>>> additional comment can be found in the patch.
>>> 
>>> Thanks,
>>> Wei
>>> 
>>> Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
>>> --
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>>> Operating System Research Center
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