> On 07/01/2009 09:14, "James Harper" <james.harper@xxxxxxxxxxxxxxxx>
wrote:
>
> > Travis said that the testing he did showed that the value changed
every
> > write. The 'lazy' bit works by only writing when it actually makes a
> > difference (eg don't write TPR until there is an actual interrupt
> > pending I think). It's (probably much) less efficient for the case
when
> > a lower priority interrupt interrupts what should be a higher
priority
> > interrupt (but isn't, because we haven't written TPR yet), but is
much
> > more efficient for the most common case where it doesn't get
> > interrupted. That's quite a bit more complicated than 'if new_tpr ==
> > old_tpr then write else nop'...
>
> Hmmm, you could be right. I suppose xentrace can confirm one way or
the
> other once you have it set up...
>
I am probably showing a lack of understanding about how the APIC works
here, but from a very brief look at what writing to the TPR register
does, all I can see is that it sets a value in vlapic->regs->data. Could
I just map a page from the DomU into xen and assign a byte in there as
the TPR register (one byte per CPU). I would need a new hypercall to
turn this on but that's no big deal. Or is there more to a TPR write
than just setting vlapic->regs->data?
Thanks
James
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