For some reason, the header changes necessary to support the
architectural pstate driver are not in linux-2.6.18-xen.hg.
Fix this oversight so the PowerNow! driver can compile.
Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>
diff -r fd879c0688bf arch/i386/kernel/cpu/cpufreq/powernow-k8.h
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h Fri Nov 23 16:26:56 
2007 +0000
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h Thu Nov 29 17:35:31 
2007 -0600
@@ -1,5 +1,5 @@
 /*
- * (c) 2003-2006 Advanced Micro Devices, Inc.
+#* (c) 2003-2006 Advanced Micro Devices, Inc.
 * Your use of this code is subject to the terms and conditions of the
 * GNU general public license version 2. See "COPYING" or
 * http://www.gnu.org/licenses/gpl.html
@@ -10,6 +10,7 @@ struct powernow_k8_data {
 
 u32 numps; /* number of p-states */
 u32 batps; /* number of p-states supported on battery */
+ u32 max_hw_pstate; /* maximum legal hardware pstate */
 
 /* these values are constant when the PSB is used to determine
 * vid/fid pairings, but are modified during the ->target() call
@@ -21,8 +22,8 @@ struct powernow_k8_data {
 u32 plllock; /* pll lock time, units 1 us */
 u32 exttype; /* extended interface = 1 */
 
- /* keep track of the current fid / vid or did */
- u32 currvid, currfid, currdid;
+ /* keep track of the current fid / vid or pstate */
+ u32 currvid, currfid, currpstate;
 
 /* the powernow_table includes all frequency and vid/fid pairings:
 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
@@ -88,23 +89,14 @@ struct powernow_k8_data {
 
 /* Hardware Pstate _PSS and MSR definitions */
 #define USE_HW_PSTATE 0x00000080
-#define HW_PSTATE_FID_MASK 0x0000003f
-#define HW_PSTATE_DID_MASK 0x000001c0
-#define HW_PSTATE_DID_SHIFT 6
-#define HW_PSTATE_MASK 0x00000007
-#define HW_PSTATE_VALID_MASK 0x80000000
-#define HW_FID_INDEX_SHIFT 8
-#define HW_FID_INDEX_MASK 0x0000ff00
-#define HW_DID_INDEX_SHIFT 16
-#define HW_DID_INDEX_MASK 0x00ff0000
-#define HW_WATTS_MASK 0xff
-#define HW_PWR_DVR_MASK 0x300
-#define HW_PWR_DVR_SHIFT 8
-#define HW_PWR_MAX_MULT 3
-#define MAX_HW_PSTATE 8 /* hw pstate supports up to 8 */
+#define HW_PSTATE_MASK 0x00000007
+#define HW_PSTATE_VALID_MASK 0x80000000
+#define HW_PSTATE_MAX_MASK 0x000000f0
+#define HW_PSTATE_MAX_SHIFT 4
 #define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */
 #define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */
 #define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */
+#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */
 
 /* define the two driver architectures */
 #define CPU_OPTERON 0
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