On 26/3/07 19:50, "Ian Pratt" <Ian.Pratt@xxxxxxxxxxxx> wrote:
> On your system it appears to be a couple of microseconds out, which is
> on the high side of what we've observed. Normally you only see that kind
> of mismatch on systems with TSCs running off different crystals.
More likely a jittery chipset timer -- we've observed less-than-ideal
stability from some chipset timers, which can throw us off a bit when
independently sync'ing the TSCs (which each CPU does for its TSC
independently every couple of seconds).
 -- Keir
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