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OMAP3 + sdmmc
Hi! OMAP-guys,
Do you work sdmmc on your board? (BEAGLEBOARD, etc...)
My OVERO's sdmmc works with some changes now.
Current status is:
- 8bit width not support yet.
- CRC error happen when block I/O, if SMC_CAPS_SINGLE_ONLY without.
I don't know this reason.
- Board-dependent card detect and write protect not yet.
- DMA not support yet.
- Power control not yet. (Required regulator(TWL) driver)
- And very noisy when boot time. :)
If you need sdmmc on your omap board then you can try with my patch.
Or wait more days. :)
Thanks,
--
kiyohara
? arch/arm/omap/omapiic.c
? arch/arm/omap/omapiicreg.h
Index: dev/sdmmc/sdhc.c
===================================================================
RCS file: /cvsroot/src/sys/dev/sdmmc/sdhc.c,v
retrieving revision 1.31
diff -u -r1.31 sdhc.c
--- dev/sdmmc/sdhc.c 13 Sep 2012 21:44:50 -0000 1.31
+++ dev/sdmmc/sdhc.c 13 Oct 2012 09:45:19 -0000
@@ -403,6 +403,7 @@
else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS))
saa.saa_clkmin /= 16;
saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP;
+saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; /* XXXX */
if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE))
saa.saa_caps |= SMC_CAPS_8BIT_MODE;
if (ISSET(caps, SDHC_HIGH_SPEED_SUPP))
@@ -625,6 +626,9 @@
struct sdhc_host *hp = (struct sdhc_host *)sch;
int r;
+ if (hp->sc->sc_vendor_card_detect)
+ return (*hp->sc->sc_vendor_card_detect)(hp->sc);
+
mutex_enter(&hp->host_mtx);
r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
mutex_exit(&hp->host_mtx);
@@ -641,6 +645,9 @@
struct sdhc_host *hp = (struct sdhc_host *)sch;
int r;
+ if (hp->sc->sc_vendor_write_protect)
+ return (*hp->sc->sc_vendor_write_protect)(hp->sc);
+
mutex_enter(&hp->host_mtx);
r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
mutex_exit(&hp->host_mtx);
@@ -695,8 +702,16 @@
* Enable bus power. Wait at least 1 ms (or 74 clocks) plus
* voltage ramp until power rises.
*/
+#if 0
HWRITE1(hp, SDHC_POWER_CTL,
(vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER);
+#else
+HWRITE1(hp, SDHC_POWER_CTL, HREAD1(hp, SDHC_POWER_CTL) & ~(SDHC_BUS_POWER |
(SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)));
+sdmmc_delay(1);
+ HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT));
+ sdmmc_delay(1);
+ HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER);
+#endif
sdmmc_delay(10000);
/*
@@ -760,13 +775,11 @@
/* No divisor found. */
return false;
} else {
- for (div = 1; div <= 256; div *= 2) {
- if ((hp->clkbase / div) <= freq) {
- *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT;
- //freq = hp->clkbase / div;
- return true;
- }
- }
+ if (hp->sc->sc_clksft != 0)
+ *divp = (hp->clkbase / freq) << hp->sc->sc_clksft;
+ else
+ *divp = (hp->clkbase / freq) << SDHC_SDCLK_DIV_SHIFT;
+ return true;
}
/* No divisor found. */
return false;
@@ -782,6 +795,7 @@
struct sdhc_host *hp = (struct sdhc_host *)sch;
u_int div;
u_int timo;
+ int16_t reg;
int error = 0;
#ifdef DIAGNOSTIC
bool present;
@@ -809,7 +823,7 @@
goto out;
}
} else {
- HWRITE2(hp, SDHC_CLOCK_CTL, 0);
+ HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
if (freq == SDMMC_SDCLK_OFF)
goto out;
}
@@ -826,7 +840,9 @@
HWRITE4(hp, SDHC_CLOCK_CTL,
div | (SDHC_TIMEOUT_MAX << 16));
} else {
- HWRITE2(hp, SDHC_CLOCK_CTL, div);
+ reg = HREAD2(hp, SDHC_CLOCK_CTL);
+ reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE);
+ HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);
}
/*
@@ -931,8 +947,11 @@
static int
sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on)
{
+ struct sdhc_host *hp = (struct sdhc_host *)sch;
+
+ if (hp->sc->sc_vendor_rod)
+ return (*hp->sc->sc_vendor_rod)(hp->sc, on);
- /* Nothing ?? */
return 0;
}
@@ -1031,6 +1050,15 @@
cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4);
cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8);
cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12);
+ if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) {
+ cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
+ (cmd->c_resp[1] << 24);
+ cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
+ (cmd->c_resp[2] << 24);
+ cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
+ (cmd->c_resp[3] << 24);
+ cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
+ }
}
}
mutex_exit(&hp->host_mtx);
Index: dev/sdmmc/sdhcvar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/sdmmc/sdhcvar.h,v
retrieving revision 1.8
diff -u -r1.8 sdhcvar.h
--- dev/sdmmc/sdhcvar.h 21 Jul 2012 16:14:05 -0000 1.8
+++ dev/sdmmc/sdhcvar.h 13 Oct 2012 09:45:20 -0000
@@ -45,9 +45,15 @@
#define SDHC_FLAG_HAVE_CGM 0x0080 /* Netlogic XLP */
#define SDHC_FLAG_NO_LED_ON 0x0100 /* LED_ON unsupported in
HOST_CTL */
#define SDHC_FLAG_HOSTCAPS 0x0200 /* No device provided
capabilities */
+#define SDHC_FLAG_RSP136_CRC 0x0400 /* Resp 136 with CRC and
end-bit */
uint32_t sc_clkbase;
+ int sc_clksft; /* Shifts for SDCLK */
uint32_t sc_caps;/* attachment provided capabilities */
+
+ int (*sc_vendor_rod)(struct sdhc_softc *, int);
+ int (*sc_vendor_write_protect)(struct sdhc_softc *);
+ int (*sc_vendor_card_detect)(struct sdhc_softc *);
};
/* Host controller functions called by the attachment driver. */
Index: arch/arm/omap/files.omap2
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/omap/files.omap2,v
retrieving revision 1.15
diff -u -r1.15 files.omap2
--- arch/arm/omap/files.omap2 5 Sep 2012 00:19:59 -0000 1.15
+++ arch/arm/omap/files.omap2 13 Oct 2012 09:45:20 -0000
@@ -109,6 +109,10 @@
attach omapfb at obio
file arch/arm/omap/omapfb.c omapfb
+device omapiic: i2cbus
+attach omapiic at obio
+file arch/arm/omap/omapiic.c omapiic
+
# these bus space methods are not bus-specific ...
#
file arch/arm/omap/omap_nobyteacc_space.c emifs | gpmc
Index: arch/arm/omap/omap3_sdhc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/omap/omap3_sdhc.c,v
retrieving revision 1.1
diff -u -r1.1 omap3_sdhc.c
--- arch/arm/omap/omap3_sdhc.c 12 Jul 2012 03:08:26 -0000 1.1
+++ arch/arm/omap/omap3_sdhc.c 13 Oct 2012 09:45:21 -0000
@@ -51,6 +51,10 @@
static int obiosdhc_match(device_t, cfdata_t, void *);
static void obiosdhc_attach(device_t, device_t, void *);
+static int obiosdhc_rod(struct sdhc_softc *, int);
+static int obiosdhc_write_protect(struct sdhc_softc *);
+static int obiosdhc_card_detect(struct sdhc_softc *);
+
struct obiosdhc_softc {
struct sdhc_softc sc;
bus_space_tag_t sc_bst;
@@ -85,16 +89,20 @@
{
struct obiosdhc_softc * const sc = device_private(self);
struct obio_attach_args * const oa = aux;
- int error;
+ int error, timo;
sc->sc.sc_dmat = oa->obio_dmat;
sc->sc.sc_dev = self;
//sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
- sc->sc.sc_flags |= SDHC_FLAG_HAVE_CGM;
sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
+ sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
sc->sc.sc_host = sc->sc_hosts;
sc->sc.sc_clkbase = 96000; /* 96MHZ */
+ sc->sc.sc_clksft = 6;
+ sc->sc.sc_vendor_rod = obiosdhc_rod;
+ sc->sc.sc_vendor_write_protect = obiosdhc_write_protect;
+ sc->sc.sc_vendor_card_detect = obiosdhc_card_detect;
sc->sc_bst = oa->obio_iot;
error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
@@ -111,6 +119,30 @@
aprint_naive(": SDHC controller\n");
aprint_normal(": SDHC controller\n");
+{
+bus_space_tag_t t2t;
+bus_space_handle_t t2h;
+t2t = sc->sc_bst;
+if (bus_space_map(t2t, 0x48002000, 0x1000, 0, &t2h) == 0) {
+// DEVCONF0=0x5000000(b24), PBIAS_LITE=0xb87(b9,b2,b1)
+ printf("%s: DEVCONF0=0x%x, PBIAS_LITE=0x%x\n", __func__,
bus_space_read_4(t2t, t2h, 0x274), bus_space_read_4(t2t, t2h, 0x520));
+ bus_space_unmap(t2t, t2h, 0x1000);
+}
+}
+printf("%s: MMCHS_SYSCONFIG=0x%x, MMCHS_SYSSTATUS=0x%x, MMCHS_CON=0x%x,
HCTL=0x%x, SYSCTL=0x%x\n", __func__, bus_space_read_4(sc->sc_bst, sc->sc_bsh,
MMCHS_SYSCONFIG), bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS),
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL));
+ /* MMCHS Soft reset */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
+ SYSCONFIG_SOFTRESET);
+ timo = 3000000; /* XXXX 3 sec. */
+ while (timo--) {
+ if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
+ SYSSTATUS_RESETDONE)
+ break;
+ delay(1);
+ }
+ if (timo == 0)
+ aprint_error_dev(self, "Soft reset timeout\n");
+
sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
sdhc_intr, &sc->sc);
if (sc->sc_ih == NULL) {
@@ -128,6 +160,85 @@
error);
goto fail;
}
+printf("%s: Re: MMCHS_SYSCONFIG=0x%x, MMCHS_SYSSTATUS=0x%x, MMCHS_CON=0x%x,
HCTL=0x%x, SYSCTL=0x%x\n", __func__, bus_space_read_4(sc->sc_bst, sc->sc_bsh,
MMCHS_SYSCONFIG), bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS),
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL));
+
+{
+ /* Set SDVS 1.8v and DTW 1bit mode */
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL,
+ SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_OD);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
SDHC_INTCLK_ENABLE | SDHC_SDCLK_ENABLE);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL) |
SDHC_BUS_POWER << 8);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
(sc->sc.sc_clkbase / 150) << 6);
+printf("%s: Re: HCTL=0x%x, SYSCTL=0x%x, MMCHS_CON=0x%x\n", __func__,
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON));
+}
+
+#if 1
+{
+ /*
+ * 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
+ * from 'OMAP35x Applications Processor Technical Reference Manual'.
+ *
+ * During the INIT procedure, the MMCHS controller generates 80 clock
+ * periods. In order to keep the 1ms gap, the MMCHS controller should
+ * be configured to generate a clock whose frequency is smaller or
+ * equal to 80 KHz.
+ */
+ uint32_t clkd, stat;
+ int n;
+
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) &
~SDHC_SDCLK_ENABLE);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) &
~0x0000ffc0);
+ clkd = sc->sc.sc_clkbase / 80;
+ n = 1;
+ while (clkd & ~0x3ff) {
+ clkd >>= 1;
+ n <<= 1;
+ }
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
(clkd << 6));
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
SDHC_SDCLK_ENABLE);
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
+ for (; n > 0; n--) {
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh,
+ SDHC_TRANSFER_MODE, 0x00000000);
+ timo = 3000000; /* XXXX 3 sec. */
+ stat = 0;
+ while (!(stat & SDHC_COMMAND_COMPLETE)) {
+ stat = bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh,
+ SDHC_NINTR_STATUS);
+ if (--timo == 0)
+ break;
+ delay(1);
+ }
+ if (timo == 0)
+ aprint_error_dev(self, "INIT Procedure timeout\n");
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh,
+ SDHC_NINTR_STATUS, stat);
+ }
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) &
~SDHC_SDCLK_ENABLE);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) &
~0x0000ffc0);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
0x0000a000);
+ bus_space_write_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL,
+ bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL) |
SDHC_SDCLK_ENABLE);
+printf("%s: Re2: HCTL=0x%x, SYSCTL=0x%x, MMCHS_CON=0x%x\n", __func__,
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_HOST_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_sdhc_bsh, SDHC_CLOCK_CTL),
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON));
+}
+#endif
+
return;
fail:
@@ -137,3 +248,36 @@
}
bus_space_unmap(sc->sc_bst, sc->sc_bsh, oa->obio_size);
}
+
+static int
+obiosdhc_rod(struct sdhc_softc *sc, int on)
+{
+ struct obiosdhc_softc *ssc = (struct obiosdhc_softc *)sc;
+ uint32_t con;
+
+ con = bus_space_read_4(ssc->sc_bst, ssc->sc_bsh, MMCHS_CON);
+ if (on)
+ con |= CON_OD;
+ else
+ con &= ~CON_OD;
+ bus_space_write_4(ssc->sc_bst, ssc->sc_bsh, MMCHS_CON, con);
+
+ return 0;
+}
+
+static int
+obiosdhc_write_protect(struct sdhc_softc *sc)
+{
+
+ /* Maybe board dependent, using GPIO. */
+ return 0; /* XXXXXXX */
+}
+
+static int
+obiosdhc_card_detect(struct sdhc_softc *sc)
+{
+
+printf("%s: in\n", __func__);
+ /* Maybe board dependent, using GPIO. */
+ return 1; /* XXXXXXXX */
+}
Index: arch/arm/omap/omap3_sdmmcreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/omap/omap3_sdmmcreg.h,v
retrieving revision 1.1
diff -u -r1.1 omap3_sdmmcreg.h
--- arch/arm/omap/omap3_sdmmcreg.h 12 Jul 2012 03:08:26 -0000 1.1
+++ arch/arm/omap/omap3_sdmmcreg.h 13 Oct 2012 09:45:21 -0000
@@ -37,4 +37,38 @@
#define OMAP3_SDMMC_SDHC_OFFSET 0x100
#define OMAP3_SDMMC_SDHC_SIZE 0x100
+
+#define MMCHS_SYSCONFIG 0x010 /* System Configuration */
+# define SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
+# define SYSCONFIG_CLOCKACTIVITY_FCLK (2 << 8)
+# define SYSCONFIG_CLOCKACTIVITY_ICLK (1 << 8)
+# define SYSCONFIG_ENAWAKEUP (1 << 2)
+# define SYSCONFIG_SOFTRESET (1 << 1)
+# define SYSCONFIG_AUTOIDLE (1 << 0)
+#define MMCHS_SYSSTATUS 0x014 /* System Status */
+# define SYSSTATUS_RESETDONE (1 << 0)
+#define MMCHS_CSRE 0x024 /* Card status response error */
+#define MMCHS_SYSTEST 0x028 /* System Test */
+#define MMCHS_CON 0x02c /* Configuration */
+# define CON_CLKEXTFREE (1 << 16)
+# define CON_PADEN (1 << 15) /* Ctrl Pow for MMC */
+# define CON_OBIE (1 << 14) /* Out-of-Band Intr */
+# define CON_OBIP (1 << 13) /*O-of-B Intr Polarity*/
+# define CON_CEATA (1 << 12) /* CE-ATA */
+# define CON_CTPL (1 << 11) /* Ctrl Power dat[1] */
+# define CON_DVAL_33US (0 << 9) /* debounce
filter val*/
+# define CON_DVAL_231US (1 << 9) /* debounce filter val*/
+# define CON_DVAL_1MS (2 << 9) /* debounce filter val*/
+# define CON_DVAL_8_4MS (3 << 9) /* 8.4ms */
+# define CON_WPP (1 << 8) /* Write protect pol */
+# define CON_CDP (1 << 7) /*Card detect polarity*/
+# define CON_MIT (1 << 6) /* MMC interrupt cmd */
+# define CON_DW8 (1 << 5) /* 8-bit mode */
+# define CON_MODE (1 << 4) /* SYSTEST mode */
+# define CON_STR (1 << 3) /* Stream command */
+# define CON_HR (1 << 2) /* Broadcast host rsp */
+# define CON_INIT (1 << 1) /* Send init stream */
+# define CON_OD (1 << 0) /* Card open drain */
+#define MMCHS_PWCNT 0x030 /* Power counter */
+
#endif
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