Re: Trivia question
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- Subject: Re: Trivia question
- From: eric koorn <eric.koorn@...>
- Date: 2014年4月30日 21:49:25 +0200
REXX uses do ... end, were they are optional for some single statement
control structures.
VHDL does not use begin for most of its constructions.
--
Ciao, Eric