NACA Seal
A scientific study of the problems of
digital engineering for space flight systems,
with a view to their practical solution.
PRESENTATIONS
Title, Authors, Reference, Link
Abstract, Summary, Conclusions
Design of Memory Systems for Spaceborne Computers
Flight Software Workshop 2007 (FSW-07) November 5-6, 2007
Laurel, MD
Abstract
Memory devices are classified and criteria for their
reliable usage are discussed. Historical memory systems are analyzed
from the 1960s through the present. Based on these lessons, the Lunar
Orbiter Laser Altimeter (LOLA) memory system was designed.
Additionally, the design of the LOLA flight software is described.
"Exploring the Planets: A Design Engineer's View and Travels"
October 8, 2006
Abstract:
This talk will discuss several spacecraft and the instruments on
them that either visited or are en route to Mercury, Venus, the Moon, Mars,
Jupiter, Saturn, and Pluto. Along with images of these deep space bodies,
there will be pictures of the spacecraft and some of the electronics which
made them work. The discussion will lso show how technology has changed from
the manned lunar program of the 1960s through today.
This talk will be a look “under the hood” from the point of view of
a design engineer participating in these missions. Along with the highlights
and excitement, some of the challenges will be discussed.
Single Event Upset and Hardening in 0.15オm Antifuse-Based FPGA
J.J. Wang, W. Wong, S. Wolday, B. Cronquist, J. McCollum, R. Katz, and I. Kleyner
Presented at IEEE NSREC 2003, Monterey, CA
nsrec_2003.ppt
nsrec_2003_portrait.ppt
Abstract
The single event effects of a 0.15オm antifuse-based field programmable gate array
(FPGA) are investigated by heavy-ion beam test and computer simulation. Single event
upsets of user flip-flop, clock, control logic, and embedded SRAM are identified and
mitigation methods are proposed.
Programmed Logic Devices (PLDs) and Complex Electronic Hardware
Will Struck
FAA Transport Airplane Directorate
Transport Standards Staff
ceh_pld2_faa.pdf
Introduction
Objective is to present current policy and practices associated with the assurance of
programmed logic devices (PLD), application specific integrated circuits (ASIC) and
complex electronic hardware (CEH) used in aircraft applications.
Single Event Effects of a FLASH-based FPGA
J. J. Wang, Brian Cronquist, John McCollum - Actel Corporation
Rich Katz, Igor Kleyner (OSC) - NASA/GSFC
Rocky Koga - The Aerospace Corporation
Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA
April 23-25, 2002 (April 22, 2002)
see02_flash.pdf
see02_flash.ppt
Outline
- Device and Technology
- Architecture
- Beam Tests and Results
- Conclusions
- ProASIC offers a high-density, re-programmable, and non-volatile
programmable logic solution to high reliability market.
- However, at this moment:
- ProASIC is not suitable for space-flight application due to its SEL sensitivity at
moderate LETTH.
- But for avionics, the heavy ion and proton testing data show that it is immune to
neutrons.
Reliable Design (MSFC)
Abstract
"Advanced Design: Designing for
Reliability, A Micro-Course"
Presented June 11
th, 2001 @ NASA Marshall Space
Flight Center
Logic_Course.ppt
Abstract
"Fundamentals of Digital
Engineering: Digital Logic, A Micro-Course"
Presented May 21
st, 2001 @ NASA Goddard Space Flight Center
"The Failure of a Small Satellite and the Loss of a Space Science Mission"
wire_updated_2005.ppt
Abstract
On March 4, 1999, the Wide-Field Infrared Explorer
(WIRE) was launched from Vandenberg Air Force Base on a Pegasus XL launch vehicle into a
540 km orbit with a planned mission duration of four months. WIRE was designed to conduct
a deep infrared, extra galactic science survey 500 times more sensitive than the Infrared
Astronomy Satellite (IRAS) Faint Source Catalog. The instrument consists of a
cryogenically cooled, 30-centimeter telescope and all associated electronics designed to
detect faint astronomical sources in two infrared wavelength bands.
The WIRE launch was nominal. Shortly after launch, ground
commands were transmitted to perform a planned secondary venting of the secondary hydrogen
tank. The next pass showed that the spacecraft was tumbling at increasing rate, ultimately
spinning up to 60 rpm. Within 36 hours of launch, the instrument's 4-month supply of
cryogen was completely exhausted. The WIRE scientific mission was declared lost on March
8, 1999.
The root cause of the WIRE mission loss is a digital logic design
error in the instrument pyro electronics box, which inadvertently caused the cover to be
ejected. The transient performance of components was not adequately considered in the box
design resulting in the inadvertent pyrotechnic device firing during the initial pyro
electronics box power-up. The results from the investigation into the failure mechanism
will be discussed; that is, how did the mission fail.
An equally important question is why did the mission fail.
Spacecraft systems go through a variety of analyses, simulations, tests, and reviews.
These will be discussed showing why the error resulted in a mishap on-orbit.
A review of launcher and spacecraft performance and failures in
the industry over the last decade will be reviewed. Trends will be presented and
discussed.
nsrec2k_pstr_h.PDF
nsrec2k_pstr_v.PDF
"Single-Event-Transient in Clock Buffer
Circuit Induced Soft Errors in Antifuse-Based FPGA" - NSREC 2000
Note: Two
files. One has the horizontally oriented charts; the other the vertically oriented
ones. (Aug 1, 2000).
nsrec00_galileo_full.ppt
"Analysis, Design, and Performance of
Electronics In a Deep Space, High Radiation Environment" - NSREC 2000 (Aug 1, 2000)
nepp2000.pdf
nepp2000.ppt
"New and Existing
Microelectronics Technologies" - NEPP 2000. Note that the .ppt file is smaller
and will download faster. (Aug 1, 2000).
C0_Katz_S.ppt
"FPGAs in Space Environment and Design
Techniques" - MAPLD 1999
Effects_Poster_NSREC99.PDF
The
Effects of Architecture and Process on the Hardness of Programmable Technologies -
Presented at IEEE NSREC, 1999.
Abstract
Architecture and process, combined, significantly affect the hardness of programmable
technologies. The effects of high energy ions, ferroelectric memory architectures, shallow
trench isolation are investigated. A detailed latchup study has been performed.
SW_Poster.PDF
The
Impact of Software and CAE Tools on SEU in Field Programmable Gate Arrays -
Presented at IEEE NSREC 1999
Abstract
Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have
grown substantially in size over the past few years, causing designers to work at a higher
conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing
the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS)
CAE tools can produce unreliable circuit designs when the device is used in a radiation
environment and a flip-flop is upset. At a lower level, software can be used to improve
the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology
and on-chip delay, parasitic resistive, and capacitive circuit elements.
A better quality version will be posted in a day or
two. rk
nsrec98_www.PDF
IEEE NSREC '98
Presentation: "Current Radiation Issues for
Programmable Elements and Devices."
Abstract:
State
of the art programmable devices are utilizing advanced processing technologies,
non-standard circuit structures, and unique electrical elements in
"commercial-off-the-shelf" (COTS)-based devices. The most recent technologies
allow programmable devices to be used in more performance-driven applications by the
spacecraft designer. This paper will show that the above factors, coupled with the systems
application environment, have a strong interplay which affect the radiation hardness of
programmable devices and have resultant system impacts.
This paper will focus on three
specific characteristics of COTS-based FPGAs in the radiation environment: reliability of
the unprogrammed, biased antifuse for heavy ions (rupture) and the radiation-hardened,
high-speed antifuse, logic upset manifesting itself as clock upset, and configuration
upset. Additionally, general radiation characteristics of advanced technologies will be
examined along with a discussion of future trends as commercial technology moves ahead.
Testing and qualification issues concerning programmables will be discussed.
Manufacturers’ modifications to their COTS-based and their impact on future
programmable devices devices will be analyzed .
MPTB_COTS2_BW.pdf
"STRV-1d SEE Flight
Experiments : Digital Electronics and Optocouplers," Presented at the SEE Symposium,
April, 1998. This posting has the first part on the Digital Electronics and the
Technologies Being Flown. The presentation has been modified for monochrome
printing. (.pdf 788 kbytes)
SEE98_BW_Final.pdf
"Sub-micron FPGA/ASIC Evaluation and SEE Issues" Presented at the SEE
Symposium, April, 1998. The presentation has been modified for monochrome
printing. (.pdf 1031 kbytes)
nsrec97.pdf
"Radiation
Effects on Field Programmable Technologies," IEEE NSREC 1997. (.pdf 771 kbytes).
irps97onopaper.pdf
"Characterization
and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and
High-Density Field-Programmable Gate Arrays," International Reliability
Physics Symposium, 1997.
ieee94_presentation.pdf
"SEU Hardening of FPGAs for Space
Applications and Device Characterization," IEEE NSREC, 1994. (.pdf 1563 kbytes -)
scanned).
Abstract:
SEU hardening techniques for FPGAs w/ circuit designs for Actel devices. Discussion
of antifuse rupture for ONO antifuses with heavy ions. SEU, SEL, and TID
characterizations for Act 1 and 2 devices.
JJ_see_sym_96.PDF
Improved SEE
Susceptibility of Radiation-Hardened ONO-Antifuse FPGA
Abstract:
Topics include: RH1280; Single Event Dielectric Rupture
(SEDR); Single Event Latch-Up (SEL); Single Event Upset (SEU)
http://radhome.gsfc.nasa.gov
NASA/GSFC Radiation Effects Home Page
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Last Revised:
February 03, 2010
Web Grunt: Richard Katz
